From patchwork Mon Jan 18 04:11:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 365452 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp1910994jap; Sun, 17 Jan 2021 20:13:01 -0800 (PST) X-Google-Smtp-Source: ABdhPJwI42jeg+BqCjX53uJc0xibCx6bpXi8TJ7JGUK6ajAdFiNxMkrfLgfDZnquEae8q+aXf34d X-Received: by 2002:a50:d484:: with SMTP id s4mr17895775edi.13.1610943181348; Sun, 17 Jan 2021 20:13:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610943181; cv=none; d=google.com; s=arc-20160816; b=C5ftdLIXUXOwvy3QPFUw9X/TocoQuTOPlifYGiobTl64W0SXNcDfDwDztk2NnK8oEe h5o36kkyzLVmFCsgWYf83PBDyfiQtL4YOwC5cgBpBGXkLv7lBZGW0XCdxDul2XH9UWD6 1L1uUZkH6rx+Qc8RKn6ziOBnCOmCUPgmetMtvmlcjL18rOK1lAJv08xu0mcBQFeHNs25 GcTrd4S5v4mkzy/zV7c5BPARwUe3vs78HNrDaxoYThLTx0d00JazVFr2Zonxn9PuMsjS n1uOWnR3sTB6dg5P3vgs/gd7bG2Hplb+P/zdUDEX8ss6xbotF2FqdcdiwytgDevda32n RWlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=dJSz008Gr3fMyHCiz6o58NLkvxxf8SsrpAa4i2B5A9Y=; b=06KOyZTfvD9d7AeTZNFlMBOXDzkHq7bOsRDdg6YTry4fbWh3Z19oyKPJuT0wrEkU4u RrGZRpubLWoRo46xNmI7y2ifd9myUxkUWG39Haigo37Z7bsUPACn/uCdb81KHOnP8DWT i2qiA6LD8l/95XCWJjsOCpDRYTpQKxC3+1gLdLjSolBLo8s1b0EAPV/Plw4UdYXNRrYI HxOSMv+RDTQj5n11EDqOnfxf/NlCn62F8ztMzrGnR1kcpaVIXFfFHGx0/va9FdPjGriK PGJi4qdSTB7O3LZIPQWBJycChb7HcHNN0xL0OZh83+C8UVcJhyR1qdvi9A1ZqQrqnkUN zs1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lsrqoPBr; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id bd1si7208708edb.168.2021.01.17.20.13.01; Sun, 17 Jan 2021 20:13:01 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lsrqoPBr; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730997AbhARENA (ORCPT + 6 others); Sun, 17 Jan 2021 23:13:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726624AbhAREM7 (ORCPT ); Sun, 17 Jan 2021 23:12:59 -0500 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 35B86C061574 for ; Sun, 17 Jan 2021 20:12:19 -0800 (PST) Received: by mail-pl1-x62c.google.com with SMTP id q4so7924258plr.7 for ; Sun, 17 Jan 2021 20:12:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=dJSz008Gr3fMyHCiz6o58NLkvxxf8SsrpAa4i2B5A9Y=; b=lsrqoPBrRDbShsY2EoTnFVgI9pXnwxl02VqP5w3FhW5fQzc16+sBDocMJ8OyX2aLoI 0Tx0I5lflR0vERpEC14lV6hjWrwWa+GULn+I1VAB/j/ovtUeAfkmxUHqk1oe5diVmYO5 MuCbyArZqKwFk/mgaP6hn6zXn1dcBrj42a7ZPZX8mGQ9tMTsXUhleB6TQ9ZyORGF5C/N I8jUAXgyRMcmGp+W+PGqiW4n8tbsXatrPEBnJbhDRIb4pumnzrF8bpueoRbDGV/d3umv 8gsoE9O3KPQus6sg0HaLO09lrxjc3jUqv6H6WZ/HMrBB2/TTf5P8TUQ6WOVw6UgogcGR ZyrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=dJSz008Gr3fMyHCiz6o58NLkvxxf8SsrpAa4i2B5A9Y=; b=hPVHBY4iYfvE9SUKnzPvaXjiXyysQgeONwaBvx2HZVBiLx1qVOgwo2aaM/RzQBdvJ/ iU9OmQ9FsgI6CDSmbeSmnft9tQu3g14FkrorSUs2RAax57J3kB87Ab7397d98CTxhZRj wh1Cskvw4BCDA7Gc01Jy536rpL1/cis9vC+1Q5aB6/lOywHVK3I8btT9AwiDIwsErnrY OXIp0FQnjatXD0W9jbiMeUtKCHSfjoJKYJtOuBFuphHF1HLE01ram9lOQ3HSkFlMMzUA sCZtDqNoxZTTrWZjbe9BM9imSV0DGsvapLWAXsJTW1163K8j1KFxWDP4++UOc81dSRrb XNWw== X-Gm-Message-State: AOAM533m1oeu+4dK7HGZclv5oayiXQEf2BeiMdZgz6G94QN1rMDUkeFr 66yL14CGWt9UDfVeUl0NeWDM X-Received: by 2002:a17:903:230b:b029:dd:7cf1:8c33 with SMTP id d11-20020a170903230bb02900dd7cf18c33mr24507515plh.31.1610943138692; Sun, 17 Jan 2021 20:12:18 -0800 (PST) Received: from localhost.localdomain ([103.77.37.182]) by smtp.gmail.com with ESMTPSA id h15sm6727319pja.4.2021.01.17.20.12.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jan 2021 20:12:17 -0800 (PST) From: Manivannan Sadhasivam To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, jassisinghbrar@gmail.com Cc: viresh.kumar@linaro.org, ulf.hansson@linaro.org, bjorn.andersson@linaro.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 0/5] Add APCS support for SDX55 Date: Mon, 18 Jan 2021 09:41:51 +0530 Message-Id: <20210118041156.50016-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hello, This series adds APCS mailbox and clock support for SDX55. The APCS IP in SDX55 provides IPC and clock functionalities. Hence, mailbox support is added to the "qcom-apcs-ipc-mailbox" driver and a dedicated clock driver "apcs-sdx55" is added. Also, the clock to the APCS block is coming from 3 different sources: 1. Board XO 2. Fixed rate GPLL0 3. A7 PLL First source is from crystal osc, second is from GCC and third one is a separate clock source. Hence, a dedicated clk driver is added for the A7 PLL as well. Apart from the mailbox support, another intention of this series is to add the CPUFreq support to SDX55 platform. Since there is no dedicated hardware IP in SDX55 to do CPUFreq duties, this platform makes use of the clock and regulators directly via cpufreq-dt driver. The trick here is attaching the power domain to cpudev. Usually the power domains for the target device is attached in the bus driver or in the dedicated device drivers. But in this case, there is no dedicated CPUFreq driver nor a bus driver. After discussing with Viresh, I concluded that A7 PLL driver might be the best place to do this! But this decision is subject to discussion, hence added Ulf and Viresh to this series. Thanks, Mani Changes in v3: * Incorporated review comments from Stephen for APCS clk driver and Rob for APCS DT binding Changes in v2: * Modified the max_register value as per the SDX55 IPC offset in mailbox driver. Manivannan Sadhasivam (5): dt-bindings: mailbox: Add binding for SDX55 APCS mailbox: qcom: Add support for SDX55 APCS IPC dt-bindings: clock: Add Qualcomm A7 PLL binding clk: qcom: Add A7 PLL support clk: qcom: Add SDX55 APCS clock controller support .../devicetree/bindings/clock/qcom,a7pll.yaml | 51 ++++++ .../mailbox/qcom,apcs-kpss-global.yaml | 33 ++++ drivers/clk/qcom/Kconfig | 17 ++ drivers/clk/qcom/Makefile | 2 + drivers/clk/qcom/a7-pll.c | 100 ++++++++++++ drivers/clk/qcom/apcs-sdx55.c | 149 ++++++++++++++++++ drivers/mailbox/qcom-apcs-ipc-mailbox.c | 7 +- 7 files changed, 358 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,a7pll.yaml create mode 100644 drivers/clk/qcom/a7-pll.c create mode 100644 drivers/clk/qcom/apcs-sdx55.c -- 2.25.1