From patchwork Sat Jan 16 03:27:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhen Lei X-Patchwork-Id: 364670 Delivered-To: patch@linaro.org Received: by 2002:a02:ccad:0:0:0:0:0 with SMTP id t13csp422208jap; Fri, 15 Jan 2021 19:33:23 -0800 (PST) X-Google-Smtp-Source: ABdhPJzCOSlVexbWXKw9LO91MW7457IfseoE7Tr69k64eqClgAbWJJ5HS5c4zrR9QkeHXrVuCmGj X-Received: by 2002:a17:906:a00a:: with SMTP id p10mr11045002ejy.312.1610768003323; Fri, 15 Jan 2021 19:33:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1610768003; cv=none; d=google.com; s=arc-20160816; b=0ZZ9RBm7CFwpo0pua5xYLP7FlAfkauNdyBrBHWinwczDZCtcVe7NZ7xHtTJIuLUN+Z IYNROD0jWYYeGLOWjpuVuO01kcU1F/NdlOb4mQZb3WIFew7yJpAEIrh6tPjtYSVRNNh9 Ka5Q9njEh1B0gNmoFiTbgvnTL2/1gYVAidBVFeUn3HAFgU5zUduXmtiozZ8dyvQpSrxB YNCg66lxQP1NIqkG73MFwD/K4k48gE2JniUQcOLAklSRI5+bFyoQzIe2uXDl9fZ+BYWm bu8CxsYpHV/2eJKZv8P/JKZk9I7aV2+HXEmeURj3mmE4si+WSmDgrE28sIn0Upb5qmZf TeXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from; bh=QHEr2MUjpcixj+ZyBwM5YgYVuyaszjg1dbsvrkO+/w0=; b=H1YgTtoGA4HvqVfVTowkBYIAiFlWyZjboq6yKtH2VFc2AGTglSnOAf5/pN0aWzw//z 2ynUlKSxgduGcZHfmUyXJ13bsvhfOp3y59zSvsUlF4AM+uepEtKuiCNlmdVxdkbBTpcp QJA8aM1noP8woBaxa94Jk+IW83gY4e2nrKCjd7yN7tQ6LZi4Ai53zbgyrPrt2lrnpfJy y0fjWgXlFF5RctFWpAJuLfFhn+gxg5vcE5eP1ugxHX4zqD3D3rGNJdUTCzELxQ6XgLBy vGAJoHmRq+QvFSSQMQCeqxXYRiFKzNqISzVGxNEB5FhT+hQjDi8xF2FDPeVuBjYkluCb LnsA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id q3si4755042ejb.483.2021.01.15.19.33.23; Fri, 15 Jan 2021 19:33:23 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729282AbhAPDcC (ORCPT + 6 others); Fri, 15 Jan 2021 22:32:02 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:11025 "EHLO szxga05-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726778AbhAPDcB (ORCPT ); Fri, 15 Jan 2021 22:32:01 -0500 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4DHk8751XTzj7Pt; Sat, 16 Jan 2021 11:30:15 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.176.220) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.498.0; Sat, 16 Jan 2021 11:31:08 +0800 From: Zhen Lei To: Russell King , Greg Kroah-Hartman , Will Deacon , "Haojian Zhuang" , Arnd Bergmann , Rob Herring , Wei Xu , devicetree , linux-arm-kernel , linux-kernel CC: Zhen Lei Subject: [PATCH v5 0/4] ARM: Add support for Hisilicon Kunpeng L3 cache controller Date: Sat, 16 Jan 2021 11:27:36 +0800 Message-ID: <20210116032740.873-1-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.174.176.220] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org v4 --> v5: 1. Add SoC macro ARCH_KUNPENG50X, and the Kunpeng L3 cache controller only enabled on that platform. 2. Require the compatible string of the Kunpeng L3 cache controller must have a relevant name on a specific SoC. For example: compatible = "hisilicon,kunpeng509-l3cache", "hisilicon,kunpeng-l3cache"; v3 --> v4: Rename the compatible string from "hisilicon,l3cache" to "hisilicon,kunpeng-l3cache". Then adjust the file name, configuration option name, and description accordingly. v2 --> v3: Add Hisilicon L3 cache controller driver and its document. That's: patch 2-3. v1 --> v2: Discard the middle-tier functions and do silent narrowing cast in the outcache hook functions. For example: -static void l2c220_inv_range(unsigned long start, unsigned long end) +static void l2c220_inv_range(phys_addr_t pa_start, phys_addr_t pa_end) { + unsigned long start = pa_start; + unsigned long end = pa_end; v1: Do cast phys_addr_t to unsigned long by adding a middle-tier function. For example: -static void l2c220_inv_range(unsigned long start, unsigned long end) +static void __l2c220_inv_range(unsigned long start, unsigned long end) { ... } +static void l2c220_inv_range(phys_addr_t start, phys_addr_t end) +{ + __l2c220_inv_range(start, end); +} Zhen Lei (4): ARM: LPAE: Use phys_addr_t instead of unsigned long in outercache hooks ARM: hisi: add support for Kunpeng50x SoC dt-bindings: arm: hisilicon: Add binding for Kunpeng L3 cache controller ARM: Add support for Hisilicon Kunpeng L3 cache controller .../arm/hisilicon/kunpeng-l3cache.yaml | 40 +++++ arch/arm/include/asm/outercache.h | 6 +- arch/arm/mach-hisi/Kconfig | 8 + arch/arm/mm/Kconfig | 10 ++ arch/arm/mm/Makefile | 1 + arch/arm/mm/cache-feroceon-l2.c | 15 +- arch/arm/mm/cache-kunpeng-l3.c | 153 ++++++++++++++++++ arch/arm/mm/cache-kunpeng-l3.h | 30 ++++ arch/arm/mm/cache-l2x0.c | 50 ++++-- arch/arm/mm/cache-tauros2.c | 15 +- arch/arm/mm/cache-uniphier.c | 6 +- arch/arm/mm/cache-xsc3l2.c | 12 +- 12 files changed, 317 insertions(+), 29 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/kunpeng-l3cache.yaml create mode 100644 arch/arm/mm/cache-kunpeng-l3.c create mode 100644 arch/arm/mm/cache-kunpeng-l3.h -- 2.26.0.106.g9fadedd