From patchwork Tue Jan 5 15:46:41 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vinod Koul X-Patchwork-Id: 356872 Delivered-To: patch@linaro.org Received: by 2002:a17:906:4755:0:0:0:0 with SMTP id j21csp230640ejs; Tue, 5 Jan 2021 07:47:38 -0800 (PST) X-Google-Smtp-Source: ABdhPJxSWSQXiCIlKQJ01bni7ZLdpTtibJBV/FXeQidvIxBM89f7U286nDLdP2fgagk0HJxUOWJK X-Received: by 2002:a50:8163:: with SMTP id 90mr371337edc.142.1609861658908; Tue, 05 Jan 2021 07:47:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1609861658; cv=none; d=google.com; s=arc-20160816; b=Odh/iOSwO6S6ARdDRAQEriYI86gocGWQuQbu3/pMQ/mbvDCTswSV9wM2kNbhCwQKhZ e096COye4p9aSkMgy8xZaR6wm3uAOZo6ebsehktfzHU2cCSNtDGa6I6ePhfGhSddZe9X MtKvpTfPLJLfSq+AyszLBTDmlzcOlsSxyLhGvOCzQlAEYvP7DD1tNttS3b0TXdIu6Y39 uN8og8KoO3P2pdddXWdbrHw950R4qj9prnClWg+3VvKs91DbWvSjBPKMnqSF+8JQq9st N9Lf4VqOeSy9gdt0q+6yP+tqThdk8JFLdumGJTZoLouISCd//xNVgOc/pLvyDy1EXZDc p5WA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=N5EwmPh7ZiUT8GA9XjZCybyxwSUwNLitnstQkZsOw7A=; b=MxgzmRl56J3CHjZnDziummf600fpCa7j3zEJlwpuDliF0rmYtPclnNM2LsXM5iOeEN VaqTmJ1fAwwsXyYAeEPJHYxG4R23i098BLZvmJWvYAwoYbe5kh1R+HbOytBc+zp1LGvc tfrZwbCuPuxrAJYXJngDMOnvwzhn/GFw6P/SX5lsPylVZBLxw1f4Hym6Qvusp3tPQLW1 ZN+QAbk5OzwwB1IzFmmqUbyUvelUln+jmobIT/r9QXAE1IbmJ9IktzsTUPgzPidx9apZ vLXUAV7RoO2CIawPeoBXrpM6Fj55F1J2xA/syYVuivcuLVVoKMm1vSNTFuyG/gtauWwD 59nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=WBnhjteX; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e23si29202453ejd.730.2021.01.05.07.47.38; Tue, 05 Jan 2021 07:47:38 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=WBnhjteX; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728428AbhAEPri (ORCPT + 6 others); Tue, 5 Jan 2021 10:47:38 -0500 Received: from mail.kernel.org ([198.145.29.99]:34566 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728307AbhAEPrh (ORCPT ); Tue, 5 Jan 2021 10:47:37 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 4342122BF3; Tue, 5 Jan 2021 15:46:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1609861617; bh=QM0PNbL6zQp9vWGkUHxqfDJNae8+Wq35ku+Qa+rO3mQ=; h=From:To:Cc:Subject:Date:From; b=WBnhjteXRzovuldguMqi3552P5uZOIAcYDES3fRjzd5dAWHhfxXq64w5YOENhCWbq Rx64h1KDogDyI+A+E3O5D2qTePZenSr72X1oSZaTERJn7MeVs2974FRk1nRreG1Gdp FbiBzGjwQufEZ84CwaG/cZCe5ISFjirmGIH1hEQialmaV0k/b13ipxUpJPxyyAG7/Q 50K8geXjMyjO0KPPfzUgRiDjztoiZeoMS5vXC0mfRU6AutFMbBZ94JgKFR9nob6BKe hGMJUWZRc5lRuKnAnMYw+ljB/syLtyo2UKZQEtFo7YQEcPuTaSR8W6zqHRZiBBGPms rBKCLU7f2DslA== From: Vinod Koul To: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org, Bjorn Andersson , Vinod Koul , Andy Gross , Michael Turquette , Rob Herring , Taniya Das , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/4] Add clock drivers for SM8350 Date: Tue, 5 Jan 2021 21:16:41 +0530 Message-Id: <20210105154645.217998-1-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds gcc clock controller drivers for the controller found in SM8350 SoC Changes in v3: - Drop rpmh clk patches applied - Add a new patch to replace regval with val as suggested by Stephen - Fix comments for new Lucid 5LPE PLL: sort new defines by BIT numbers, fix comments, use alpha_pll_check_rate_margin(), rework clk_lucid_5lpe_pll_postdiv_set_rate() logic - Add power domains and optional clocks in bindings - Fix comments for gcc sm8350 driver: clean includes used, use only .fw_name for clocks defined in DT, use floor ops for sdcc clocks, remove critical clocks and enable them in probe, add comments for clks using BRANCH_HALT_SKIP and BRANCH_HALT_DELAY Changes in v2: - Add r-b from Bjorn - Add the gcc_qupv3_wrap_1_{m|s}_ahb_clk and gcc_qupv3_wrap1_s5_clk Vinod Koul (2): clk: qcom: clk-alpha-pll: replace regval with val dt-bindings: clock: Add SM8350 GCC clock bindings Vivek Aknurwar (2): clk: qcom: clk-alpha-pll: Add support for Lucid 5LPE PLL clk: qcom: gcc: Add clock driver for SM8350 .../bindings/clock/qcom,gcc-sm8350.yaml | 96 + drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-alpha-pll.c | 237 +- drivers/clk/qcom/clk-alpha-pll.h | 4 + drivers/clk/qcom/gcc-sm8350.c | 3790 +++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sm8350.h | 261 ++ 7 files changed, 4387 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml create mode 100644 drivers/clk/qcom/gcc-sm8350.c create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8350.h -- 2.26.2