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[23.128.96.18]) by mx.google.com with ESMTP id w2si9948757edx.591.2020.12.08.04.15.27; Tue, 08 Dec 2020 04:15:28 -0800 (PST) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Xi09IcSD; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729419AbgLHMO5 (ORCPT + 6 others); Tue, 8 Dec 2020 07:14:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729342AbgLHMO5 (ORCPT ); Tue, 8 Dec 2020 07:14:57 -0500 Received: from mail-pf1-x442.google.com (mail-pf1-x442.google.com [IPv6:2607:f8b0:4864:20::442]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CB8E3C061793 for ; Tue, 8 Dec 2020 04:14:16 -0800 (PST) Received: by mail-pf1-x442.google.com with SMTP id w6so13743063pfu.1 for ; Tue, 08 Dec 2020 04:14:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=fXCEVGsIRfU3fvhpZQTmT+oIgD4SahenV2U/sWf5U20=; b=Xi09IcSDA1msKP7AAF7eX00q2D6OwK6gSBuUGpA2wuYwcJlM9NUbRRx7MdK3LWlVe1 am4ut+xc79MskNZWxHte1/VTzVh4mvZvLfpCjfwMTu7IYDzPyPIWWo9WV6OnUmNOYDFC 4IuhYwBaDIumRMtGV5QsUNXyuYO4ltqk8Odtk44VrEHDJMpttLRzeYOYzpIXbO1T+cs0 alyC22DY/WF+LswKNkyqRxrBHP3cI7PI3I0K64CwXpVwSQo5OAa2Cwbj3/YX8eCNi6pj wqztEifvFqaWUfIQz03Jr7h7PvZyjqXv+OFtGkqGnZSXdqvA3LxocB3QuT5+23h+zYUf ORow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=fXCEVGsIRfU3fvhpZQTmT+oIgD4SahenV2U/sWf5U20=; b=EjN/NfPc1idPjFC+XbGFMtZK0CNskGGxA69kTPhW/H+2g0TloKFZcFd2NZArpZ9D/k am9dL0fcILP9lH4J5I+gmkAfYUHUQBjymFI4cHpdIyUP0GS8zd1Z4/6tmILAUqbrtzo6 Zu3np2E1lxE9CYXOvuaXaXulSxDdPGOVH7c91WOL/PRnIu5x4aCVn75LnD6hTwTCqWX6 8L6baTfpQwG6+b9kAQUXgGEgG5GDBPZTke01svC00OYre1YCq6IxcjEj1m3FmE+iIG59 F9kbjYbQFtsAK4w4CJn1Ifbc2l1ekNiuDf+18TLlz6q+vfyw26Xbg4XCPWUG4OKkjEN5 sq1w== X-Gm-Message-State: AOAM531WEDrULozgY3cPhpt+RCHB6zUGYcLwx0XsKtgJZQ1oPhcnLH8C LKVz816hYQLmwV0rj59irddn X-Received: by 2002:a05:6a00:2302:b029:198:4459:e6c9 with SMTP id h2-20020a056a002302b02901984459e6c9mr20125297pfh.33.1607429655887; Tue, 08 Dec 2020 04:14:15 -0800 (PST) Received: from localhost.localdomain ([103.59.133.81]) by smtp.gmail.com with ESMTPSA id v3sm3489889pjn.7.2020.12.08.04.14.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Dec 2020 04:14:15 -0800 (PST) From: Manivannan Sadhasivam X-Google-Original-From: Manivannan Sadhasivam To: lorenzo.pieralisi@arm.com Cc: agross@kernel.org, bjorn.andersson@linaro.org, svarbanov@mm-sol.com, bhelgaas@google.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, devicetree@vger.kernel.org, truong@codeaurora.org, Manivannan Sadhasivam Subject: [PATCH v6 0/3] Add PCIe support for SM8250 SoC Date: Tue, 8 Dec 2020 17:43:59 +0530 Message-Id: <20201208121402.178011-1-mani@kernel.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hello, This series adds PCIe support for Qualcomm SM8250 SoC with relevant PHYs. There are 3 PCIe instances on this SoC each with different PHYs. The PCIe controller and PHYs are mostly comaptible with the ones found on SDM845 SoC, hence the old drivers are modified to add the support. This series has been tested on RB5 board with QCA6391 chipset connected onboard. Thanks, Mani Changes in v6: * Dropped phy patches and rebased on top of pci/dwc branch * Collected reviews from Bjorn Changes in v5: * Added Review tags from Rob * Cleaned up the bdf to sid patch after discussing with Tony Changes in v4: * Fixed an issue with tx_tbl_sec in PHY driver Changes in v3: * Rebased on top of phy/next * Renamed ops_sm8250 to ops_1_9_0 to maintain uniformity Changes in v2: * Fixed the PHY and PCIe bindings * Introduced secondary table in PHY driver to abstract out the common configs. * Used a more generic way of configuring BDF to SID mapping * Dropped ATU change in favor of a patch spotted by Rob Manivannan Sadhasivam (3): dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC PCI: qcom: Add SM8250 SoC support PCI: qcom: Add support for configuring BDF to SID mapping for SM8250 .../devicetree/bindings/pci/qcom,pcie.txt | 6 +- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 96 +++++++++++++++++++ 3 files changed, 101 insertions(+), 2 deletions(-) -- 2.25.1