From patchwork Mon Oct 5 09:12:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 314047 Delivered-To: patch@linaro.org Received: by 2002:a92:d603:0:0:0:0:0 with SMTP id w3csp1127919ilm; Mon, 5 Oct 2020 02:13:04 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzCMd5XkuffMUUgfNn4ORl1Y7C2310BEtgc5JZSG5RKaRdJhQnucn4IUctS+YyynAyBpcqu X-Received: by 2002:a17:906:3e48:: with SMTP id t8mr14349056eji.104.1601889184449; Mon, 05 Oct 2020 02:13:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1601889184; cv=none; d=google.com; s=arc-20160816; b=PSD3wqxotAnwmDDZWpOkvYLhQq0IZr7A3xEzF7ZtrHSeccxUBg1vXev5PsW3AHjZkI i88lgTTJEU3TA9UI4Cc5RByfMAnrxIL6BT84JVdKV89ywRaaoilxj+rF+ymv9sEtk3Ar Vhc0riceJlvF1v8ealcdxW1XqG8AcIfUCce60UqKAzWn2JWfOQOw318HPrGRs9K++aRk 8vCJZN8yiAoJZlI6u2sbpiTzkQpbzamtL5D9/VB/CfgTFgE6SQMDkz8cvBCzq4MK9UR5 7I0WAVipBcyWIX9lwSoFuo1V83yOdo0bMeejLKzoRCngBfqKlF6EuctJmGKEe4H6WFz3 uvPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:message-id:date:subject:cc:to:from :dkim-signature; bh=ogtuZFvmTG1HNJ4mpeUW7o3oDnuWDjMGFWxAfAyP1zo=; b=MhAih6usKsZB9VenWj/oEhw8TC9HaxMmG6CsdJTr8F9Gs1xHn0fQ53q98pKISwNB1a BBZaz4FFAa9j3Ru5HuaUW1Ujg192lWH35zsQM3sKk0dEnrtvlPScidFJQNe6RwfVwPkT CMvLlJ/30jMHx8Xj4HyJomXv5baSkmqj3VfWcMP+tsgfRRCBa2n6rTjceeYgxvzR1Wxu YHq5c5lCizVMyHpAWV454n68USE/oMLaijH9x95kaFexKs26oTBSdQo8Dzo+mLi3FBz8 d9kfn1EooeXq+dhqSDX5uHuUQjfBiLDCPOASsnqU4eo/+UMopbof3m1HXutCjBkiZqsj Hapg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pXBuoTsP; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id e18si6912489ejk.628.2020.10.05.02.13.04; Mon, 05 Oct 2020 02:13:04 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pXBuoTsP; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726006AbgJEJND (ORCPT + 6 others); Mon, 5 Oct 2020 05:13:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725887AbgJEJND (ORCPT ); Mon, 5 Oct 2020 05:13:03 -0400 Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E4ACC0613CE for ; Mon, 5 Oct 2020 02:13:03 -0700 (PDT) Received: by mail-pg1-x544.google.com with SMTP id g29so5624082pgl.2 for ; Mon, 05 Oct 2020 02:13:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=ogtuZFvmTG1HNJ4mpeUW7o3oDnuWDjMGFWxAfAyP1zo=; b=pXBuoTsPuRad3vIUhnovelwcdfQU07Dv8Z+Qy++jDhwhdR0Emie8AuwmaT7EjATyD5 LWJXWDJX4zrMY4bLBJicioD/na0mCDYuq2dpjz78gJTkkhbAnc0A/SVV0NzAk4fqDYcQ IYDhyezYAoB09Vfd5DndUUTKk+Oq4RxVgefyh+Xt3yYV5l8DzssfHTFxlg/8Ads2xP0d PmUwHzb9HLUSGWdfcXu3hEhFqWRPHxTcgvkj69O9mERUIjTKu/ntyJjo5YyncEcHfMa8 T+t+XDrm5I3Rr72jXjfdcF/VGNw6ZH4eVTCOWu/sy14AoLNStskyKOGtqeqaT7HJc2eS O31w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ogtuZFvmTG1HNJ4mpeUW7o3oDnuWDjMGFWxAfAyP1zo=; b=LaIkHcQ2dhEM7fLkPSp18NABCOkuWTQu57J/H0JYYAZ4nqvGyURB9tg8zW9A7qCeh6 3GLydaLnFxz5RKP1JxrbUO+N4onVIEvAZyKmfiQQfO74rQE56P8QNVBqIMp6XQ5QopD5 fGrBNDne8EvHg71MlJdz4lMcC/Jr76ZSHDQegrwvu9iFc/PK/+lYdazwFgcrTchzX8r2 +NPj6LvbdhElFYOGOH145P6AI8UI62s7iMzYm+q4PX5sYVWx8vy5Mq8PNOoM5R8uIRTw Y7FDFHPp4xR+cqqmcd/oMPwhYgymM52xhGI9HSkvqMnslM20iIWBo67dYh1xP9jrtL9o 0PmA== X-Gm-Message-State: AOAM5334jpju3cGvlFuf9t/nFNVFw4Hgnrvl31fyhWz5xJtGHQcmKYCs 3bfmoZ18qzpHH9tMLOHjCFwV X-Received: by 2002:a63:c40a:: with SMTP id h10mr9314528pgd.210.1601889182847; Mon, 05 Oct 2020 02:13:02 -0700 (PDT) Received: from localhost.localdomain ([103.59.133.81]) by smtp.googlemail.com with ESMTPSA id c7sm11255028pfj.84.2020.10.05.02.12.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Oct 2020 02:13:02 -0700 (PDT) From: Manivannan Sadhasivam To: agross@kernel.org, bjorn.andersson@linaro.org, kishon@ti.com, vkoul@kernel.org, robh@kernel.org Cc: svarbanov@mm-sol.com, bhelgaas@google.com, lorenzo.pieralisi@arm.com, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, mgautam@codeaurora.org, devicetree@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v3 0/5] Add PCIe support for SM8250 SoC Date: Mon, 5 Oct 2020 14:42:31 +0530 Message-Id: <20201005091236.31770-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hello, This series adds PCIe support for Qualcomm SM8250 SoC with relevant PHYs. There are 3 PCIe instances on this SoC each with different PHYs. The PCIe controller and PHYs are mostly comaptible with the ones found on SDM845 SoC, hence the old drivers are modified to add the support. This series has been tested on RB5 board with QCA6390 chipset connected onboard. NOTE: This series functionally depends on the following patch: https://lore.kernel.org/linux-arm-kernel/1599814203-14441-3-git-send-email-hayashi.kunihiko@socionext.com/ I've dropped a similar patch in v2. Thanks, Mani Changes in v3: * Rebased on top of phy/next * Renamed ops_sm8250 to ops_1_9_0 to maintain uniformity Changes in v2: * Fixed the PHY and PCIe bindings * Introduced secondary table in PHY driver to abstract out the common configs. * Used a more generic way of configuring BDF to SID mapping * Dropped ATU change in favor of a patch spotted by Rob Manivannan Sadhasivam (5): dt-bindings: phy: qcom,qmp: Add SM8250 PCIe PHY bindings phy: qcom-qmp: Add SM8250 PCIe QMP PHYs dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC PCI: qcom: Add SM8250 SoC support PCI: qcom: Add support for configuring BDF to SID mapping for SM8250 .../devicetree/bindings/pci/qcom,pcie.txt | 6 +- .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 6 + drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 149 ++++++++++ drivers/phy/qualcomm/phy-qcom-qmp.c | 281 +++++++++++++++++- drivers/phy/qualcomm/phy-qcom-qmp.h | 18 ++ 6 files changed, 455 insertions(+), 6 deletions(-) -- 2.17.1