mbox series

[v2,0/5] Add PCIe support for SM8250 SoC

Message ID 20200930150925.31921-1-manivannan.sadhasivam@linaro.org
Headers show
Series Add PCIe support for SM8250 SoC | expand

Message

Manivannan Sadhasivam Sept. 30, 2020, 3:09 p.m. UTC 
Hello,

This series adds PCIe support for Qualcomm SM8250 SoC with relevant PHYs.
There are 3 PCIe instances on this SoC each with different PHYs. The PCIe
controller and PHYs are mostly comaptible with the ones found on SDM845
SoC, hence the old drivers are modified to add the support.

This series has been tested on RB5 board with QCA6390 chipset connected
onboard.

NOTE: This series functionally depends on the following patch:
https://lore.kernel.org/linux-arm-kernel/1599814203-14441-3-git-send-email-hayashi.kunihiko@socionext.com/

I've dropped a similar patch in v2.

Thanks,
Mani

Changes in v2:

* Fixed the PHY and PCIe bindings
* Introduced secondary table in PHY driver to abstract out the common configs.
* Used a more generic way of configuring BDF to SID mapping
* Dropped ATU change in favor of a patch spotted by Rob

Manivannan Sadhasivam (5):
  dt-bindings: phy: qcom,qmp: Add SM8250 PCIe PHY bindings
  phy: qcom-qmp: Add SM8250 PCIe QMP PHYs
  dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC
  PCI: qcom: Add SM8250 SoC support
  PCI: qcom: Add support for configuring BDF to SID mapping for SM8250

 .../devicetree/bindings/pci/qcom,pcie.txt     |   6 +-
 .../devicetree/bindings/phy/qcom,qmp-phy.yaml |   6 +
 drivers/pci/controller/dwc/Kconfig            |   1 +
 drivers/pci/controller/dwc/pcie-qcom.c        | 149 ++++++++++
 drivers/phy/qualcomm/phy-qcom-qmp.c           | 278 +++++++++++++++++-
 drivers/phy/qualcomm/phy-qcom-qmp.h           |  18 ++
 6 files changed, 454 insertions(+), 4 deletions(-)

-- 
2.17.1

Comments

Stanimir Varbanov Sept. 30, 2020, 9:56 p.m. UTC | #1 
Hi Mani,

On 9/30/20 6:09 PM, Manivannan Sadhasivam wrote:
> The PCIe IP on SM8250 SoC is similar to the one used on SDM845. Hence

> the support is added reusing the members of ops_2_7_0. The key

> difference between ops_2_7_0 and ops_sm8250 is the config_sid callback,

> which will be added in successive commit.

> 

> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

> ---

>  drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++

>  1 file changed, 11 insertions(+)

> 

> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c

> index 3aac77a295ba..44db91861b47 100644

> --- a/drivers/pci/controller/dwc/pcie-qcom.c

> +++ b/drivers/pci/controller/dwc/pcie-qcom.c

> @@ -1359,6 +1359,16 @@ static const struct qcom_pcie_ops ops_2_7_0 = {

>  	.post_deinit = qcom_pcie_post_deinit_2_7_0,

>  };

>  

> +/* Qcom IP rev.: 1.9.0 */

> +static const struct qcom_pcie_ops ops_sm8250 = {


This breaks the policy compatible -> ops_X_Y_Z. Could you introduce new
method config_sid and check into for compatible qcom,pcie-sm8250 string
there?

> +	.get_resources = qcom_pcie_get_resources_2_7_0,

> +	.init = qcom_pcie_init_2_7_0,

> +	.deinit = qcom_pcie_deinit_2_7_0,

> +	.ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,

> +	.post_init = qcom_pcie_post_init_2_7_0,

> +	.post_deinit = qcom_pcie_post_deinit_2_7_0,

> +};

> +

>  static const struct dw_pcie_ops dw_pcie_ops = {

>  	.link_up = qcom_pcie_link_up,

>  };

> @@ -1476,6 +1486,7 @@ static const struct of_device_id qcom_pcie_match[] = {

>  	{ .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },

>  	{ .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },

>  	{ .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },

> +	{ .compatible = "qcom,pcie-sm8250", .data = &ops_sm8250 },

>  	{ }

>  };

>  

> 


-- 
regards,
Stan