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[23.128.96.18]) by mx.google.com with ESMTP id r14si1561463edb.14.2020.09.24.00.19.35; Thu, 24 Sep 2020 00:19:36 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727084AbgIXHTf (ORCPT + 6 others); Thu, 24 Sep 2020 03:19:35 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:45504 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726902AbgIXHTf (ORCPT ); Thu, 24 Sep 2020 03:19:35 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id B8A3414C03520B5C6204; Thu, 24 Sep 2020 15:19:32 +0800 (CST) Received: from thunder-town.china.huawei.com (10.174.177.253) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Thu, 24 Sep 2020 15:19:25 +0800 From: Zhen Lei To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , "Alexey Brodkin" , Vineet Gupta , devicetree , linux-snps-arc , linux-kernel CC: Zhen Lei , Sebastian Hesselbarth , Haoyu Lv , Libin , Kefeng Wang Subject: [PATCH v6 0/6] irqchip: dw-apb-ictl: support hierarchy irq domain Date: Thu, 24 Sep 2020 15:17:48 +0800 Message-ID: <20200924071754.4509-1-thunder.leizhen@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.174.177.253] X-CFilter-Loop: Reflected Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org v5 --> v6: 1. add Reviewed-by: Rob Herring for Patch 4. 2. Some modifications are made to Patch 5: 1) add " |" for each "description:" property if its content exceeds one line, to tell the yaml keep the "newline" character. 2) add "..." to mark the end of the yaml file. 3) Change the name list of maintainers to the author of "snps,dw-apb-ictl.txt" maintainers: - - Marc Zyngier + - Sebastian Hesselbarth 4) add "maxItems: 1" for property "reg". 5) for property "interrupts": interrupts: - minItems: 1 - maxItems: 65 + maxItems: 1 6) move below descriptions under the top level property "description:" description: | Synopsys DesignWare provides interrupt controller IP for APB known as dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt controller in some SoCs, e.g. Hisilicon SD5203. + The interrupt sources map to the corresponding bits in the interrupt + registers, i.e. + - 0 maps to bit 0 of low interrupts, + - 1 maps to bit 1 of low interrupts, + - 32 maps to bit 0 of high interrupts, + - 33 maps to bit 1 of high interrupts, + - (optional) fast interrupts start at 64. + For more details of 2-6), please refer https://lkml.org/lkml/2020/9/24/13 v4 --> v5: 1. Add WARN_ON(1) in set_handle_irq() if !GENERIC_IRQ_MULTI_HANDLER 2. Convert "snps,dw-apb-ictl.txt" to "snps,dw-apb-ictl.yaml" 3. Fix the errors detected by "snps,dw-apb-ictl.yaml" on arch/arc v3 --> v4: 1. remove "gc->chip_types[0].chip.irq_eoi = irq_gc_noop;", the "chip.irq_eoi" hook is not needed by handle_level_irq(). Thanks for Marc Zyngier's review. 2. Add a new patch: define an empty function set_handle_irq() if !GENERIC_IRQ_MULTI_HANDLER to avoid compilation error on arch/arc system. v2 --> v3: 1. change (1 << hwirq) to BIT(hwirq). 2. change __exception_irq_entry to __irq_entry, so we can "#include " instead of "#include ". Ohterwise, an compilation error will be reported on arch/csky. drivers/irqchip/irq-dw-apb-ictl.c:20:10: fatal error: asm/exception.h: No such file or directory 3. use "if (!parent || (np == parent))" to determine whether it is primary interrupt controller. 4. make the primary interrupt controller case also use function handle_level_irq(), I used handle_fasteoi_irq() as flow_handler before. 5. Other minor changes are not detailed. v1 --> v2: According to Marc Zyngier's suggestion, discard adding an independent SD5203-VIC driver, but make the dw-apb-ictl irqchip driver to support hierarchy irq domain. It was originally available only for secondary interrupt controller, now it can also be used as primary interrupt controller. The related dt-bindings is updated appropriately. Add "Suggested-by: Marc Zyngier ". Add "Tested-by: Haoyu Lv ". v1: The interrupt controller of SD5203 SoC is VIC(vector interrupt controller), it's based on Synopsys DesignWare APB interrupt controller (dw_apb_ictl) IP, but it can not directly use dw_apb_ictl driver. The main reason is that VIC is used as primary interrupt controller and dw_apb_ictl driver worked for secondary interrupt controller. So add a new driver: "hisilicon,sd5203-vic". Zhen Lei (6): genirq: define an empty function set_handle_irq() if !GENERIC_IRQ_MULTI_HANDLER irqchip: dw-apb-ictl: prepare for support hierarchy irq domain irqchip: dw-apb-ictl: support hierarchy irq domain dt-bindings: dw-apb-ictl: support hierarchy irq domain dt-bindings: dw-apb-ictl: convert to json-schema ARC: [dts] fix the errors detected by dtbs_check .../interrupt-controller/snps,dw-apb-ictl.txt | 31 -------- .../interrupt-controller/snps,dw-apb-ictl.yaml | 74 +++++++++++++++++++ arch/arc/boot/dts/axc001.dtsi | 2 +- arch/arc/boot/dts/axc003.dtsi | 2 +- arch/arc/boot/dts/axc003_idu.dtsi | 2 +- arch/arc/boot/dts/vdk_axc003.dtsi | 2 +- arch/arc/boot/dts/vdk_axc003_idu.dtsi | 2 +- drivers/irqchip/Kconfig | 2 +- drivers/irqchip/irq-dw-apb-ictl.c | 83 ++++++++++++++++++---- include/linux/irq.h | 6 ++ 10 files changed, 157 insertions(+), 49 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.yaml -- 1.8.3