From patchwork Wed May 20 12:44:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 200265 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B428CC433E0 for ; Wed, 20 May 2020 12:45:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 83DE420758 for ; Wed, 20 May 2020 12:45:32 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="c3cWrTEr" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726868AbgETMpc (ORCPT ); Wed, 20 May 2020 08:45:32 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33262 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726570AbgETMpb (ORCPT ); Wed, 20 May 2020 08:45:31 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 04KCj0uD006158; Wed, 20 May 2020 07:45:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1589978700; bh=8nwhAbh5OTRkKkm30f70KfL0dIF8WSriIhQIaxxmJpc=; h=From:To:CC:Subject:Date; b=c3cWrTEriFZcDIzEnZoHtBYNDTpzG4pcB4hT1aAvivjOmT1CpuXa5nen6Y0x/4lHV jdaXxB8Z2MfdpoqbcPqbbmenJRWIASwvZ7Cfr8K025YOKWy6+aluCLzPy9DT2nMLfu 8/Jdudu8utktIk+0DbDINqQuUoCsXuqpD+SOU574= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04KCj0LG048681; Wed, 20 May 2020 07:45:00 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 20 May 2020 07:45:00 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 20 May 2020 07:45:00 -0500 Received: from lokesh-ssd.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 04KCiuvK026764; Wed, 20 May 2020 07:44:57 -0500 From: Lokesh Vutla To: Marc Zyngier , Rob Herring CC: Thomas Gleixner , Nishanth Menon , Tero Kristo , Santosh Shilimkar , Linux ARM Mailing List , Sekhar Nori , Grygorii Strashko , Peter Ujfalusi , Device Tree Mailing List , Lokesh Vutla Subject: [PATCH 00/12] irqchip: ti, sci-intr/inta: Update the dt bindings to accept different interrupt parents Date: Wed, 20 May 2020 18:14:42 +0530 Message-ID: <20200520124454.10532-1-lokeshvutla@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Marc, This is continuation of the RFC patches[0] regarding the driver updates to support for following interrupt parent connection: - INTR -> INTR - INTA -> GICv3 The current existing driver assumes that INTR is always connected to GICv3 and INTA is always connected to INTR. As discussed this change breaks the DT backward compatibility but it allows to not depend on TISCI firmware properties in DT node. IMHO, this will ensure that any future changes will not effect DT properties. [0] https://lore.kernel.org/linux-arm-kernel/20190923042405.26064-1-lokeshvutla@ti.com/ Thanks and regards, Lokesh Lokesh Vutla (12): firmware: ti_sci: Drop the device id to resource type translation firmware: ti_sci: Drop unused structure ti_sci_rm_type_map firmware: ti_sci: Add support for getting resource with subtype dt-bindings: irqchip: ti,sci-intr: Update bindings to drop the usage of gic as parent dt-bindings: irqchip: Convert ti,sci-intr bindings to yaml irqchip/ti-sci-intr: Add support for INTR being a parent to INTR dt-bindings: irqchip: ti,sci-inta: Update docs to support different parent. dt-bindings: irqchip: Convert ti,sci-inta bindings to yaml irqchip/ti-sci-inta: Add support for INTA directly connecting to GIC arm64: dts: k3-j721e: ti-sci-inta/intr: Update to latest bindings arm64: dts: k3-am65: ti-sci-inta/intr: Update to latest bindings arm64: dts: k3-am65: Update the RM resource types .../interrupt-controller/ti,sci-inta.txt | 66 -------- .../interrupt-controller/ti,sci-inta.yaml | 104 ++++++++++++ .../interrupt-controller/ti,sci-intr.txt | 82 --------- .../interrupt-controller/ti,sci-intr.yaml | 113 +++++++++++++ MAINTAINERS | 4 +- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 34 ++-- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 12 +- arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 8 +- .../arm64/boot/dts/ti/k3-am654-base-board.dts | 4 +- .../dts/ti/k3-j721e-common-proc-board.dts | 10 +- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 41 ++--- .../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 12 +- drivers/firmware/ti_sci.c | 155 ++++++++---------- drivers/irqchip/irq-ti-sci-inta.c | 90 ++++++++-- drivers/irqchip/irq-ti-sci-intr.c | 150 ++++++++++------- include/linux/soc/ti/ti_sci_protocol.h | 13 ++ 16 files changed, 527 insertions(+), 371 deletions(-) delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.txt create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml