From patchwork Wed May 6 15:14:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 201027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A69BC47257 for ; Wed, 6 May 2020 15:14:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1988020936 for ; Wed, 6 May 2020 15:14:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="UpM8Rhwj" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729393AbgEFPOu (ORCPT ); Wed, 6 May 2020 11:14:50 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:37050 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729290AbgEFPOu (ORCPT ); Wed, 6 May 2020 11:14:50 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 046FEZiO005090; Wed, 6 May 2020 10:14:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1588778075; bh=IdCq3HhGfnXfKkkCRXngzOs6oMP/9HZj8dRoQcBYPD4=; h=From:To:CC:Subject:Date; b=UpM8RhwjCOiyYW/f+2iUu+a9AQ0iY0A/4tMZ5v1PsuBxtSP9O+L77yuzPriBqmGSY 5QyLVMMh31ySXmxbUgstorR1nfMwZa4HvSw5B8RYdq4vzLzFzo5FdNZshYhWuxbuI7 pBhJji5t7BE6V4AXXrKM+HldYu2yaSlbAAElFvVk= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 046FEYnI099464 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 6 May 2020 10:14:34 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 6 May 2020 10:14:34 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 6 May 2020 10:14:34 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 046FEUg6119457; Wed, 6 May 2020 10:14:31 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Tom Joseph CC: Greg Kroah-Hartman , , , , , , Subject: [PATCH v4 00/14] Add PCIe support to TI's J721E SoC Date: Wed, 6 May 2020 20:44:15 +0530 Message-ID: <20200506151429.12255-1-kishon@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TI's J721E SoC uses Cadence PCIe core to implement both RC mode and EP mode. The high level features are: *) Supports Legacy, MSI and MSI-X interrupt *) Supports upto GEN4 speed mode *) Supports SR-IOV *) Supports multiple physical function *) Ability to route all transactions via SMMU This patch series *) Add support in Cadence PCIe core to be used for TI's J721E SoC *) Add a driver for J721E PCIe wrapper v1 of the series can be found @ [1] v2 of the series can be found @ [2] v3 of the series can be found @ [5] Changes from v3: 1) Changed the order of files in MAINTAINTERS file to fix Joe's comments 2) Fixed indentation and added Reviewed-by: Rob Herring 3) Cleaned up computing msix_tbl 4) Fixed RobH's comment on J721E driver Changes from v2: 1) Converting Cadence binding to YAML schema was done as a separate series [3] & [4]. [3] is merged and [4] is pending. 2) Included MSI-X support in this series 3) Added link down interrupt handling (only error message) 4) Rebased to latest 5.7-rc1 5) Adapted TI J721E binding to [3] & [4] Changes from v1: 1) Added DT schemas cdns-pcie-host.yaml, cdns-pcie-ep.yaml and cdns-pcie.yaml for Cadence PCIe core and included it in TI's PCIe DT schema. 2) Added cpu_addr_fixup() for Cadence Platform driver. 3) Fixed subject/description/renamed functions as commented by Andrew Murray. [1] -> http://lore.kernel.org/r/20191209092147.22901-1-kishon@ti.com [2] -> http://lore.kernel.org/r/20200106102058.19183-1-kishon@ti.com [3] -> http://lore.kernel.org/r/20200305103017.16706-1-kishon@ti.com [4] -> http://lore.kernel.org/r/20200417114322.31111-1-kishon@ti.com [5] -> http://lore.kernel.org/r/20200417125753.13021-1-kishon@ti.com Alan Douglas (1): PCI: cadence: Add MSI-X support to Endpoint driver Kishon Vijay Abraham I (13): PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error path linux/kernel.h: Add PTR_ALIGN_DOWN macro PCI: cadence: Add support to use custom read and write accessors PCI: cadence: Add support to start link and verify link status PCI: cadence: Add read/write accessors to perform only 32-bit accesses PCI: cadence: Allow pci_host_bridge to have custom pci_ops PCI: cadence: Add new *ops* for CPU addr fixup PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID register dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC PCI: j721e: Add TI J721E PCIe driver misc: pci_endpoint_test: Add J721E in pci_device_id table MAINTAINERS: Add Kishon Vijay Abraham I for TI J721E SoC PCIe .../bindings/pci/ti,j721e-pci-ep.yaml | 89 ++++ .../bindings/pci/ti,j721e-pci-host.yaml | 113 ++++ MAINTAINERS | 4 +- drivers/misc/pci_endpoint_test.c | 9 + drivers/pci/controller/cadence/Kconfig | 23 + drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pci-j721e.c | 492 ++++++++++++++++++ .../pci/controller/cadence/pcie-cadence-ep.c | 125 ++++- .../controller/cadence/pcie-cadence-host.c | 59 ++- .../controller/cadence/pcie-cadence-plat.c | 13 + drivers/pci/controller/cadence/pcie-cadence.c | 48 +- drivers/pci/controller/cadence/pcie-cadence.h | 158 +++++- include/linux/kernel.h | 1 + 13 files changed, 1093 insertions(+), 42 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml create mode 100644 drivers/pci/controller/cadence/pci-j721e.c