From patchwork Mon Mar 16 07:23:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Lu X-Patchwork-Id: 203267 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D667C18E5B for ; Mon, 16 Mar 2020 07:24:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 655CE20663 for ; Mon, 16 Mar 2020 07:24:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="TEuM7M94" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729811AbgCPHYg (ORCPT ); Mon, 16 Mar 2020 03:24:36 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:44565 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729638AbgCPHYg (ORCPT ); Mon, 16 Mar 2020 03:24:36 -0400 X-UUID: edeebb8b7704427090312173cae9ccee-20200316 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=SME2J3snLnpUKDZ+/mhvA9A9BXydvq2FK3+5529r+Aw=; b=TEuM7M9480zmjH6HOjHEjnQC2v3iyUJKS1vHVOqQ4N0JqI67LVIPLJaknbBtkI2O81gvICQ8uvzTf+4E+LinJUlyXkSk9Tx+P65Y8EIo8p7w1npEbYmKrdygg1GCWKL9liNej+Y4IFX/SXNL9pnT+VRrChi6TPagiBGz9snH55Q=; X-UUID: edeebb8b7704427090312173cae9ccee-20200316 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 628648822; Mon, 16 Mar 2020 15:24:29 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 16 Mar 2020 15:22:50 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 16 Mar 2020 15:21:29 +0800 From: Roger Lu To: Kevin Hilman , Rob Herring , Nicolas Boichat , Stephen Boyd CC: Fan Chen , HenryC Chen , YT Lee , Xiaoqing Liu , Charles Yang , Angus Lin , Mark Rutland , Matthias Brugger , Nishanth Menon , Roger Lu , , , , , Subject: [PATCH v7 0/3] PM / AVS: SVS: Introduce SVS engine Date: Mon, 16 Mar 2020 15:23:14 +0800 Message-ID: <20200316072316.7156-1-roger.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: FAAF471B3CEBE181E2299E54C03D13A8F639F8379D2227AA0B0EE8D05A49E7012000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 1. SVS driver use OPP adjust event in [1] to update OPP table voltage part. 2. SVS dts node refers to CPU opp table [2] and GPU opp table [3]. 3. SVS and thermal dts use the same thermal efuse [4]. 4. SVS dts needs PMIC regulator [5]. [1] https://patchwork.kernel.org/patch/11193513/ [2] https://patchwork.kernel.org/patch/11304935/ [3] https://patchwork.kernel.org/patch/11423009/ [4] https://patchwork.kernel.org/patch/11316495/ [5] https://patchwork.kernel.org/patch/11284617/ pending discussion on v7: - SVS sub-node architecture pending discussion in below patch. https://lore.kernel.org/patchwork/patch/1175994/ changes since v6: - svs_isr_handler() function is merged into svs_isr(). - In svs_isr(), we find which bank fires interrupt first and check this bank is suspended or not secondly. - Use memdup_user_nul() instead of copy_from_user(). - Use U32_MAX instead of "(u32)-1. - SVS needs to do resume after thermal resume in system suspend flow. Therefore, change SVS pm_ops to prepare/complete. - Add high temperature voltages compensation codes. - Add irqflags in "struct svs_platform" for supporting different SVS HW setting. - Set signed-off voltages to system when system suspend. - Add SVS HW reset flag for future SVS HW support. - Coding style refinement. Roger Lu (3): dt-bindings: soc: add mtk svs dt-bindings arm64: dts: mt8183: add svs device information PM / AVS: SVS: Introduce SVS engine .../devicetree/bindings/power/mtk-svs.txt | 76 + arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 16 + arch/arm64/boot/dts/mediatek/mt8183.dtsi | 41 + drivers/power/avs/Kconfig | 10 + drivers/power/avs/Makefile | 1 + drivers/power/avs/mtk_svs.c | 2074 +++++++++++++++++ include/linux/power/mtk_svs.h | 23 + 7 files changed, 2241 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/mtk-svs.txt create mode 100644 drivers/power/avs/mtk_svs.c create mode 100644 include/linux/power/mtk_svs.h