From patchwork Fri Jan 3 12:43:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vidya Sagar X-Patchwork-Id: 206211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52F2CC2D0C2 for ; Fri, 3 Jan 2020 12:44:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 26C9120848 for ; Fri, 3 Jan 2020 12:44:14 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="kOnlSzPm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727523AbgACMoN (ORCPT ); Fri, 3 Jan 2020 07:44:13 -0500 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:18120 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727494AbgACMoN (ORCPT ); Fri, 3 Jan 2020 07:44:13 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 03 Jan 2020 04:43:57 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 03 Jan 2020 04:44:12 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 03 Jan 2020 04:44:12 -0800 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 3 Jan 2020 12:44:12 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 3 Jan 2020 12:44:12 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.48]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Fri, 03 Jan 2020 04:44:11 -0800 From: Vidya Sagar To: , , , , , CC: , , , , , , , , , , Subject: [PATCH V2 0/5] Add support for PCIe endpoint mode in Tegra194 Date: Fri, 3 Jan 2020 18:13:59 +0530 Message-ID: <20200103124404.20662-1-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1578055437; bh=av4maRAzw0Y30U4hvGLMR0lUrFrmERz6SpyIVwF8MaU=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=kOnlSzPmwzAb6pUqs88wdbOW2ZUWJV4ffBY0mTwnSRoFzNfI92gDKcMp0aGCFFESp +ijP5z3Zo2uIew/Z9CzVcqe1X+PbgCNhk7E79XQmb14L9ftLnySjW08XIxEZQJExGw B09zwgUHj6fxtAbmgqRK8lS4baD3z88Uu3bUuZJdBfyScXIdDgG5FB+8kFVBItEam/ hpk9//f8C0+5sQytRKzY2IBEhVfho0VLJZDH93Le7Un8TyDgftAlq6UYebmtPfwaBU nk84UsVsW783Lmv11vSjGg1RWmVkZeOSrLMdAfT6OzxUdqDfaTsN1XJ+bTO3hTBNGG VRlPMhnw5xbgw== Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Tegra194 has three (C0, C4 & C5) dual mode PCIe controllers that can operate either in root port mode or in end point mode but only in one mode at a time. Platform P2972-0000 supports enabling endpoint mode for C5 controller. This patch series adds support for PCIe endpoint mode in both the driver as well as in DT. This patch series depends on the changes made for Synopsys DesignWare endpoint mode subsystem that are currently under review @ https://patchwork.kernel.org/project/linux-pci/list/?series=202211 which in turn depends on the patch made by Kishon @ https://patchwork.kernel.org/patch/10975123/ which is also under review. V2: * Addressed Thierry & Bjorn's review comments * Added EP mode specific binding documentation to already existing binding documentation file * Removed patch that enables GPIO controller nodes explicitly as they are enabled already Vidya Sagar (5): soc/tegra: bpmp: Update ABI header dt-bindings: PCI: tegra: Add DT support for PCIe EP nodes in Tegra194 PCI: tegra: Add support for PCIe endpoint mode in Tegra194 arm64: tegra: Add PCIe endpoint controllers nodes for Tegra194 arm64: tegra: Add support for PCIe endpoint mode in P2972-0000 platform .../bindings/pci/nvidia,tegra194-pcie.txt | 125 ++- .../boot/dts/nvidia/tegra194-p2972-0000.dts | 18 + arch/arm64/boot/dts/nvidia/tegra194.dtsi | 99 +++ drivers/pci/controller/dwc/Kconfig | 30 +- drivers/pci/controller/dwc/pcie-tegra194.c | 782 +++++++++++++++++- include/soc/tegra/bpmp-abi.h | 10 +- 6 files changed, 1021 insertions(+), 43 deletions(-)