From patchwork Thu Nov 28 10:46:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 180388 Delivered-To: patch@linaro.org Received: by 2002:a92:38d5:0:0:0:0:0 with SMTP id g82csp7346349ilf; Thu, 28 Nov 2019 02:47:42 -0800 (PST) X-Google-Smtp-Source: APXvYqwjv0uQ4FarPMT6nsH6+P8fc5CLDxHJPfYP+Podq6OqF+euQa+QZ7gHVAwyvQKA8ShK1Z1x X-Received: by 2002:a17:906:70d4:: with SMTP id g20mr3496231ejk.319.1574938062084; Thu, 28 Nov 2019 02:47:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1574938062; cv=none; d=google.com; s=arc-20160816; b=fC7b72uhVaAEMebohSObP76EEuws5vvQn01GstA9bT6qzVnlNmcvgqgGgXJtWRWsaP vKdeBjxPYsrHpfUR0zwrBf+M1iCXlIFrZGMnuavfPbiXpmhQ9xZqdUJSWSQbhhOUAzAJ P74zLwk0pVOFhtCfe6MDpAi63JUJ3qB6Ea7Rl76cfQumwkTaOp5PbV9Q1svQE7k2d0qE O/sU6FJaEQdVLuvHjnFA09Z/MlyfHhCCodXhH3cAjlE+J9S3pgrRqyqv9SxGKdRI5a4u c8Bh3DzlLIPNBhVCBQml4fVjmNfvciI7oGJAWX3ks0AMpHwKOXAXeq3cQLX2GO8HYffE DrCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:dkim-signature; bh=eKSU4P9KuQJ/Do7x57Iah14M9xnEYTaNHRuLpboeRuc=; b=p5ma/RoNb16VaFSHXnuXxBk2So4Ly4SDbylIZbpjeU5JCjFy0Ma/Dpk7XVYkROWKIP lr0q2/mEQ7hGlRVLsJ1G5mfDiJkymbquc4iqCgOtzKAYsmzrYQcz8ONpobQcaPAHFwnw NYAZNJS6TJlQ6+nmQAZt3rUf4ilK7RFAObiWlVUrUKq+i8GRO7JceMdPIi4YGkSObgGt 3bqhB+oDGHrxpEkxrMmK1Awt27v+8Zj1f+bslmKCgbJMTeISzmOgt78VAXiNnDo+iQPQ gtHJDHbc/WYoueKsogHhRjSDRmgIlMXrYDhPLYjntmZLXisK1pEJ7fxEC8QsM8A7Aer1 EBgg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FaLrypxI; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l10si11712321ejb.336.2019.11.28.02.47.41; Thu, 28 Nov 2019 02:47:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FaLrypxI; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726252AbfK1Krk (ORCPT + 8 others); Thu, 28 Nov 2019 05:47:40 -0500 Received: from fllv0016.ext.ti.com ([198.47.19.142]:58016 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726227AbfK1Krk (ORCPT ); Thu, 28 Nov 2019 05:47:40 -0500 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id xASAlarG096661; Thu, 28 Nov 2019 04:47:36 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1574938056; bh=eKSU4P9KuQJ/Do7x57Iah14M9xnEYTaNHRuLpboeRuc=; h=From:To:CC:Subject:Date; b=FaLrypxIqB8k7gWSrE28fq6fjmJToxV1Uayoe3XvvTov8R7neFPcB1W1/PgUpPkS0 mAZTmfu77ZbysAOMBNz4/LpsoMiwN1nKMb5He+fm65W4EZR4U0ENEsYhOJ2YvasO5u UirB8pRsa1rAr02K0kh58CSX5yPEZerUJvHxbgSc= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id xASAlaO6126286 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 28 Nov 2019 04:47:36 -0600 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Thu, 28 Nov 2019 04:47:36 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Thu, 28 Nov 2019 04:47:36 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id xASAlX3v098163; Thu, 28 Nov 2019 04:47:33 -0600 From: Kishon Vijay Abraham I To: Kishon Vijay Abraham I , Rob Herring , Anil Varughese , Roger Quadros , Jyri Sarha CC: , Subject: [PATCH v3 00/14] PHY: Add support for SERDES in TI's J721E SoC Date: Thu, 28 Nov 2019 16:16:34 +0530 Message-ID: <20191128104648.21894-1-kishon@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TI's J721E SoC uses Cadence Sierra SERDES for USB, PCIe and SGMII. TI has a wrapper named WIZ to control input signals to Sierra and Torrent SERDES. This patch series: 1) Add support to WIZ module present in TI's J721E SoC 2) Adapt Cadence Sierra PHY driver to be used for J721E SoC Changes from v2: *) Deprecate "phy_clk" binding *) Fix Rob's comment on dt bindings -> Include BSD-2-Clause license identifier -> drop "oneOf" and "items" for compatible -> Fixed "num-lanes" to include only scalar keywords -> Change to 32-bit address space for child nodes *) Rename cmn_refclk/cmn_refclk1 to cmn_refclk_dig_div/ cmn_refclk1_dig_div Changes from v1: *) Change the dt binding Documentation of WIZ wrapper to YAML format *) Fix an issue in Sierra while doimg rmmod Anil Varughese (1): phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC Kishon Vijay Abraham I (13): dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resources phy: cadence: Sierra: Use "regmap" for read and write to Sierra registers phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide phy: cadence: Sierra: Get reset control "array" for each link phy: cadence: Sierra: Check for PLL lock during PHY power on phy: cadence: Sierra: Change MAX_LANES of Sierra to 16 phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove() dt-bindings: phy: Document WIZ (SERDES wrapper) bindings phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC .../bindings/phy/phy-cadence-sierra.txt | 13 +- .../bindings/phy/ti,phy-j721e-wiz.yaml | 158 +++ drivers/phy/cadence/phy-cadence-sierra.c | 699 +++++++++++--- drivers/phy/ti/Kconfig | 15 + drivers/phy/ti/Makefile | 1 + drivers/phy/ti/phy-j721e-wiz.c | 904 ++++++++++++++++++ 6 files changed, 1651 insertions(+), 139 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml create mode 100644 drivers/phy/ti/phy-j721e-wiz.c -- 2.17.1