From patchwork Thu Oct 24 11:40:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 177408 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp2062512ill; Thu, 24 Oct 2019 04:40:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqynR/ipzp7RuTQZxO9akcYeeRI4dLZ36XbcBA8bvRwENU/iu3J1j4Il1KkNh3sL5KMln6ZI X-Received: by 2002:a05:6402:8cf:: with SMTP id d15mr41782177edz.225.1571917250750; Thu, 24 Oct 2019 04:40:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571917250; cv=none; d=google.com; s=arc-20160816; b=cUvVTXlEl+c+XtlHLjzPkoRS9kvMM5tJ+Kuf2J3kQJGaCBS/cQJJPVDd5bBr1p2mKc SgnU3oQbQKMXWAQWh7d2p6zllZN+W9+DtSNol6ZtQ8uClmPWpB+3ULqQ4hta5auiP3/e Oq9A+hEFQ4UnYagVVrux+N7AgYZjkicpXIcB6+X7aOmFL01TwWOUQ3qnQBt5Fws01hgx fXOlkWwCk7rODYnaYAe/KyCkb9WbfFkuJ2G1Rua5vS1YpngZtxF35nNk/1/sHUU26NbI O2dd2fx/TM//G8PJXgJfYgK8nboJmHFExxIn/XbudaJ5aKDMbOl2d2mZxUOE+BaHbKrr NCDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:dkim-signature; bh=y5vv5MyXJRX25aniSxbVw1jtU1e58440UmSrBui2ECI=; b=r4cSs+S1lyh5TSKXJiA3jy2OEUi/cE9zebdJsFn6d5QJ1s9uFzC3MFiS2+L09jlDnx 8joSRI5jMCAaN8/IBKoeq0hHhYDyYOOnGKFh3Lv2B8VjfQ1zXvuMmyAh8PF4ljz5NcOM GQcxmyW+5WzghEz/WZNsTRsiOl/DGFTXk3cwhDSdYPpLe6gMtYcCTnYcasDNGEOHsTFC o7ygF8yXf57ewZnQjw04OUR/NvPFfCmKE15jYGmdXSxSHPaaFRTfbQbHZFzknaqvUMNc RoGzvgs5YbaJJ9t9oP5RGb/s7Pcc+IbkHZ3xYAWyQ7nEfNGOOqwIyA8OIh+9oNPFfN0g pKVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ux+Gs+j9; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k39si11068120edb.99.2019.10.24.04.40.50; Thu, 24 Oct 2019 04:40:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ux+Gs+j9; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2438861AbfJXLku (ORCPT + 8 others); Thu, 24 Oct 2019 07:40:50 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:36458 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725283AbfJXLkt (ORCPT ); Thu, 24 Oct 2019 07:40:49 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9OBemZD088997; Thu, 24 Oct 2019 06:40:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571917248; bh=y5vv5MyXJRX25aniSxbVw1jtU1e58440UmSrBui2ECI=; h=From:To:CC:Subject:Date; b=ux+Gs+j9QZGZxLEUvi6/1r3YuacbWW+SyMGzioOL3LeUxcDfM5p9AUBy6D/L6+IvK tHo2SAIAxqgyNVZEnKpJrprcnnBKbntuhIINJPvJhlw8hVmsiP3VfHd8w9ptbM718C fOoeAUZmsaT0a45R9LIpGa+xTh3YuxJMZRxnRxAY= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9OBemRS128764 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 24 Oct 2019 06:40:48 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Thu, 24 Oct 2019 06:40:36 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Thu, 24 Oct 2019 06:40:36 -0500 Received: from lta0400828a.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9OBeiTA044238; Thu, 24 Oct 2019 06:40:44 -0500 From: Roger Quadros To: CC: , , , , , , Roger Quadros Subject: [PATCH v3 0/3] phy: cadence: j721e-wiz: Add Type-C plug flip support Date: Thu, 24 Oct 2019 14:40:39 +0300 Message-ID: <20191024114042.30237-1-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi, On J721e platform, the 2 lanes of SERDES PHY are used to achieve USB Type-C plug flip support without any additional MUX component by using a lane swap feature. However, the driver needs to know the Type-C plug orientation before it can decide whether to swap the lanes or not. This is achieved via a GPIO named DIR. Another constraint is that the lane swap must happen only when the PHY is in inactive state. This is achieved by sampling the GPIO and programming the lane swap before bringing the PHY out of reset. This series adds support to read the GPIO and accordingly program the Lane swap for Type-C plug flip support. Series must be applied on top of https://lkml.org/lkml/2019/10/23/589 cheers, -roger Changelog: v3 - Rebase on v2 of PHY series and update DT binding to yaml v2 - revise commit log of patch 1 - use regmap_field in patch 3 Roger Quadros (3): phy: cadence: Sierra: add phy_reset hook dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO phy: ti: j721e-wiz: Manage typec-gpio-dir .../bindings/phy/ti,phy-j721e-wiz.yaml | 15 ++++++ drivers/phy/cadence/phy-cadence-sierra.c | 10 ++++ drivers/phy/ti/phy-j721e-wiz.c | 48 +++++++++++++++++++ 3 files changed, 73 insertions(+) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki