From patchwork Wed Oct 23 12:57:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 177274 Delivered-To: patch@linaro.org Received: by 2002:a92:409a:0:0:0:0:0 with SMTP id d26csp687711ill; Wed, 23 Oct 2019 05:58:13 -0700 (PDT) X-Google-Smtp-Source: APXvYqw5q98SvPFNOGWoy8FC+M1HiQgnWmJ9hGYk3R27ZVEeB6maAKNweRVexJC3FHJGX4aL73Y8 X-Received: by 2002:a17:906:80cd:: with SMTP id a13mr33125499ejx.12.1571835493019; Wed, 23 Oct 2019 05:58:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1571835493; cv=none; d=google.com; s=arc-20160816; b=wptFtRyiM3Ml1xsN/TttB4bbLEZEwYn34AC7dDmcApoKLt6v5mq7Tz8sTJ662QKGx8 c/fHDvJ0cxfGoK3TdznG+q1kQR+sqcPdwwfYPQzlzjRZkniLOTfaVnHC9fCTJtE6Bo6p uPHszRWvnKcYoujOVm7fecCla0T0D7ZLJ55A7i5sjgFk0oUXeCEzjJx+uyHUUmMN2vS2 KymaUGaVQ5PRHlVUJvkCAftKjkV6PmfhTbzRUb5bQYYL8nyzIvx/HZwqIOZ8/6U9O1+V CBJGLTADOGaiB3oUFPjv0EJZkP2YUk1r5OJE2LDP7J2BpApSjuJMDT6OUWiIbujLodeY aYQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:dkim-signature; bh=sECd/uFdwzMoCMf0uldBu7VsoVmQR5rzVIKvyhIOXls=; b=b1jHzHwASGtJYHk53uAZAOrbv+EjOCpfAq4+oDprL9oCbH4covs2j8TErbS3Edl9pf OG9IT+oTzvIv0pD9j9XC9IiOFpgC+aSCjstUvl1i64oWBO9u5GGjJqOBPwgM12pFTlcY ON4VcZ0HVup3W8FkWwAQMhV4sm1/RPrO/5LynBS75VeLUqnuRr5yv9cL7Psj1hgc8SU4 FYvig+uM5cLi8R+agR2fViOwtQaDPurKLf3Bb82LwdO0BRq7VITl4SN+s5jwuDTTe9Rq /sY1SRK+YaVpfUoxyH45gSkAgDqmU0y74XEeX1G/T7+HqnVtzsLToUAx8fkVecqKzWH5 ok8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jQYWfkSP; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id w57si6320562eda.78.2019.10.23.05.58.12; Wed, 23 Oct 2019 05:58:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jQYWfkSP; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390405AbfJWM6M (ORCPT + 8 others); Wed, 23 Oct 2019 08:58:12 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:59204 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2390108AbfJWM6L (ORCPT ); Wed, 23 Oct 2019 08:58:11 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9NCw8xU047913; Wed, 23 Oct 2019 07:58:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1571835488; bh=sECd/uFdwzMoCMf0uldBu7VsoVmQR5rzVIKvyhIOXls=; h=From:To:CC:Subject:Date; b=jQYWfkSPNPOaiOhxsFdoKA5J+Vnn+jOf04vOoplZAKXCBWFZKx9zRB1mWAs0mYuAg vrp8QZyUISMIL22brq9wzHosiTowA6Ma8pMkYyUBzAPbaXYPfJoLxhWzqVgg590qb7 W6BJsbRbrdK54BGNOtW9ArYvNeFqH1c+49GWBluw= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9NCw8tn064267; Wed, 23 Oct 2019 07:58:08 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 23 Oct 2019 07:57:58 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 23 Oct 2019 07:57:58 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9NCw5o4061147; Wed, 23 Oct 2019 07:58:05 -0500 From: Kishon Vijay Abraham I To: Rob Herring , Kishon Vijay Abraham I , Roger Quadros , Jyri Sarha CC: Anil Varughese , , Subject: [PATCH v2 00/14] PHY: Add support for SERDES in TI's J721E SoC Date: Wed, 23 Oct 2019 18:27:21 +0530 Message-ID: <20191023125735.4713-1-kishon@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org TI's J721E SoC uses Cadence Sierra SERDES for USB, PCIe and SGMII. TI has a wrapper named WIZ to control input signals to Sierra and Torrent SERDES. This patch series: 1) Add support to WIZ module present in TI's J721E SoC 2) Adapt Cadence Sierra PHY driver to be used for J721E SoC Changes from v1: *) Change the dt binding Documentation of WIZ wrapper to YAML format *) Fix an issue in Sierra while doimg rmmod Anil Varughese (1): phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC Kishon Vijay Abraham I (13): dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resources phy: cadence: Sierra: Use "regmap" for read and write to Sierra registers phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide phy: cadence: Sierra: Get reset control "array" for each link phy: cadence: Sierra: Check for PLL lock during PHY power on phy: cadence: Sierra: Change MAX_LANES of Sierra to 16 phy: cadence: Sierra: Set cmn_refclk/cmn_refclk1 frequency to 25MHz phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove() dt-bindings: phy: Document WIZ (SERDES wrapper) bindings phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC .../bindings/phy/phy-cadence-sierra.txt | 13 +- .../bindings/phy/ti,phy-j721e-wiz.yaml | 159 +++ drivers/phy/cadence/phy-cadence-sierra.c | 697 +++++++++++--- drivers/phy/ti/Kconfig | 15 + drivers/phy/ti/Makefile | 1 + drivers/phy/ti/phy-j721e-wiz.c | 904 ++++++++++++++++++ 6 files changed, 1650 insertions(+), 139 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml create mode 100644 drivers/phy/ti/phy-j721e-wiz.c -- 2.17.1