From patchwork Mon Sep 16 16:14:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 173864 Delivered-To: patch@linaro.org Received: by 2002:ac9:19ad:0:0:0:0:0 with SMTP id d45csp4090433oce; Mon, 16 Sep 2019 09:15:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqx+j6gwv7ZzrDTvZkAuYsOzU8i1zGpcIdtlyr4FlFHQDOZynCsh6lkF+y3wg+80GnY5aGoc X-Received: by 2002:a17:906:7f91:: with SMTP id f17mr755973ejr.125.1568650503760; Mon, 16 Sep 2019 09:15:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1568650503; cv=none; d=google.com; s=arc-20160816; b=hRarGKPqCqPQWAQr4tPQQWMiJdYxG80Kkd/Ag9nyDNFwYjjV4dBb851XzIIXWdI74N aMWTY+PhPIEfu3ZbFydW9ZCGlnHn9gVFRozMzDUuuSd4m6SlmhnNwCQ5VxQltJVeO4xB sSPLIKQf8IKvRNW+bM6G5Mjdn5dG7yi7XoQEf/sqkE1emJT8Em4O7E9OTdksrV63pxzZ QI1j9/Z9yM4aYgn+nKWAOQszS6WWIYzPMoYIG9aZKY/bZUSoRN+vl6nu3QmHjxOMEp+G M2VLMKbsJ5KmWf7VzhJyjLfQa6EO5zl4OY84Pe1mmtQaEPSvC5IzILNa3ox8WpePT3wC m2kQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature; bh=YqI202SP9Uvm6lQD97H4g3P2DuY2a7DQ+cgjEVc1iKE=; b=BqhC7uxhzqA7w8r8Zity4TK//xsymofiBh9Ailw60rWVsNLO6H9Sa2iIhrvCGC6iOt yVthY2DMH9xfMtVgEx+EfMnxPIE0mq0qFn5QtXN74q0yvcxShAvKz7X7/ui1BaaKpkKk /meBsnKBGCePkj+uV80YLan8rtQOQdGb6AefTi+FMTBE+jJPkLdhVDIZIuwnRea1mO81 eCV2BHKn6YJO8rFUbTzJ0Zp5PWgIBOflg/N4ftcwY3kXp3jmx7vCeob8vzZzOgsYs4E7 bCdElMrD/T00iNl6NBL9cTDDJiVQYLlq6IYib4ZOrnxzABvZxrkkBeJ3E60FTBf1kM0I P2tQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TCFJ+T5V; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e16si15726416ejj.372.2019.09.16.09.15.03; Mon, 16 Sep 2019 09:15:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TCFJ+T5V; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389678AbfIPQPC (ORCPT + 8 others); Mon, 16 Sep 2019 12:15:02 -0400 Received: from mail-pf1-f195.google.com ([209.85.210.195]:43713 "EHLO mail-pf1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727296AbfIPQPC (ORCPT ); Mon, 16 Sep 2019 12:15:02 -0400 Received: by mail-pf1-f195.google.com with SMTP id a2so171010pfo.10 for ; Mon, 16 Sep 2019 09:15:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=YqI202SP9Uvm6lQD97H4g3P2DuY2a7DQ+cgjEVc1iKE=; b=TCFJ+T5VQp/PBhYSSCAmY4rWCPO61OkcTmlcfwPeLEQxWoNSKi4+kdpTZ3KgLao1bP 78YuAjmnc+fuu15yyj9WuXavFLo8vmEeWx9qRJzt2m4tH4E88ZFkNAIUws8SNjvV334h ZuPxKFcj8jmDVbVXdIPSxRMx/rCG8AD6PQ8BL784ZjC1LzJKMv4fCABTrrpjSBnufWpR ab8VVXa7At+aYgWye6PRjYBlah4HDNfLX/FlQRlnybwD/nSvKQB+0yTYJCVPvOACTUnJ Sjjwkj38yDCfOyKJfB+vFJuVLkxtLsVxSuLrzVyu4hFFuOkAkQM87YzArntp+bofj1Ef XhAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=YqI202SP9Uvm6lQD97H4g3P2DuY2a7DQ+cgjEVc1iKE=; b=p5IADg48WVKB+8oEh/p3KzhikevXxNn2SrRFc0zgVm++He/yBxCunnWKyMsp/bB/l1 spRf0aqpzhEvagmvOheY6MJ4SXszBxWRo7HUA/DUwyTG0MWKGoOIh2DD7ORq04cZJcj1 E/bAA5o6z+EItjmRzlvEnp8NGSaj+NcCv08YZJKR2efzdrYvLT2+ez2rk/vau9tpq/7k n56KOGHJXyhJn25R4+jGT3hbOKnKN9ZX3CwyPN4YlSRIYv6+T6oxFwYHZ2EWcfkcxhp0 RClpCWVwsjab0x6fk8HDPahNMvbLhxGAVMZCSgcnlWkmIawkty8i27cBQPmtYmZtzm/s Xm9A== X-Gm-Message-State: APjAAAWx88EX8xx5dIt9yLK4EnT9K64VFuOXTAp5VqO5RxnOwT0gRPBt 4KxLxEWWZRutqyvzagy/MYj/ X-Received: by 2002:a63:221f:: with SMTP id i31mr13278538pgi.251.1568650501307; Mon, 16 Sep 2019 09:15:01 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:90b:91ce:94c2:ef93:5bd:cfe8]) by smtp.gmail.com with ESMTPSA id h66sm614134pjb.0.2019.09.16.09.14.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Sep 2019 09:15:00 -0700 (PDT) From: Manivannan Sadhasivam To: sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org Cc: linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, haitao.suo@bitmain.com, darren.tsao@bitmain.com, fisher.cheng@bitmain.com, alec.lin@bitmain.com, Manivannan Sadhasivam Subject: [PATCH v5 0/8] Add Bitmain BM1880 clock driver Date: Mon, 16 Sep 2019 21:44:39 +0530 Message-Id: <20190916161447.32715-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hello, This patchset adds common clock driver for Bitmain BM1880 SoC clock controller. The clock controller consists of gate, divider, mux and pll clocks with different compositions. Hence, the driver uses composite clock structure in place where multiple clocking units are combined together. This patchset also removes UART fixed clock and sources clocks from clock controller for Sophon Edge board where the driver has been validated. Thanks, Mani Changes in v5: * Incorporated review comments from Rob on dt binding Changes in v4: * Fixed devicetree binding issue * Added ARCH_BITMAIN as the default for the clk driver Changes in v3: * Switched to clk_hw_{register/unregister} APIs * Returned clk_hw from the in-driver registration helpers Changes in v2: * Converted the dt binding to YAML * Incorporated review comments from Stephen (majority of change is switching to new way of specifying clk parents) Manivannan Sadhasivam (8): clk: Zero init clk_init_data in helpers clk: Warn if clk_init_data is not zero initialized clk: Add clk_hw_unregister_composite helper function definition dt-bindings: clock: Add devicetree binding for BM1880 SoC arm64: dts: bitmain: Add clock controller support for BM1880 SoC arm64: dts: bitmain: Source common clock for UART controllers clk: Add common clock driver for BM1880 SoC MAINTAINERS: Add entry for BM1880 SoC clock driver .../bindings/clock/bitmain,bm1880-clk.yaml | 76 ++ MAINTAINERS | 2 + .../boot/dts/bitmain/bm1880-sophon-edge.dts | 9 - arch/arm64/boot/dts/bitmain/bm1880.dtsi | 28 + drivers/clk/Kconfig | 7 + drivers/clk/Makefile | 1 + drivers/clk/clk-bm1880.c | 966 ++++++++++++++++++ drivers/clk/clk-composite.c | 13 +- drivers/clk/clk-divider.c | 2 +- drivers/clk/clk-fixed-rate.c | 2 +- drivers/clk/clk-gate.c | 2 +- drivers/clk/clk-mux.c | 2 +- drivers/clk/clk.c | 8 + include/dt-bindings/clock/bm1880-clock.h | 82 ++ 14 files changed, 1186 insertions(+), 14 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml create mode 100644 drivers/clk/clk-bm1880.c create mode 100644 include/dt-bindings/clock/bm1880-clock.h -- 2.17.1