From patchwork Sat Jun 8 19:53:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 166202 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp2157354ili; Sat, 8 Jun 2019 12:53:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqyQCvOzF7SoWtNpIef1uo+7CsdMkI60MMkyqbHLdh4urfr/D+N5A0C8bO58M1gUb8VWuMje X-Received: by 2002:a17:90a:ac0e:: with SMTP id o14mr12783803pjq.142.1560023618923; Sat, 08 Jun 2019 12:53:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560023618; cv=none; d=google.com; s=arc-20160816; b=IFobdyiwko8n2jRjqgwBbAT7k4ITVDC7DvAWOFqVYXdSPAJtLdfapnrTfJS/6Gn5SO T8/FDhARvMZFxT6xb1OebAv7rAgENIRjUf9misiYl9gY+OOQ3mPAyqHw91CMKUI2u97v ZTe7qzBvo45//RW9A8jrdso8Neqdgr10vpuhJyYylF1uZax1QphQyzWNPm6u73VnbsQ+ KhWfWD1JlgRFs78juRUZmp9yljboycKuItz5+H/bfzl+4KAlx/x5ObV7+IPqGF4vkG6y fA/D/hKEgA6nCEFE3IRrRVNGzd5wrJ2U6eBcUA5w4g12XDSUTd2PlZCmLnKbjOx1CMgN VD5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature; bh=y4R+1O2JCF2sqyz0/RUxgRqX037Zf7Xz8+zI8QsEWlE=; b=SQz9Vy/K7+8T/n5WQgwbznvg/FcG/4aK7oO3Bq6b1RmndTTpd4muBv3iWx1o0m6Vh1 FUiF+UZjWGPP5oOd5Q7ZLV7i62852Umu45/zq6jKjus3zvpAvf22T72/8JWIVO9sFn8d OU/OtN2C4rBkgs/Le2R02yeCq5c79DhWmth6D1I1YME9+8gpLatvGUeWpJqCKI6bfvRS ZyPwQSgwWFrDowSr/CZPmFCTU0k+8bjlodpUXtBKTwXa2xlgEFtHXJUsj2oQoKDD+u5U wQQlH6siPI5wNrXzw2JU+wXhlGbgWRm3aPsixlG3bJqH4hV4PIVqckNf62wvJlROayMU DDxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qmma1PwA; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c14si5207259pjr.51.2019.06.08.12.53.38; Sat, 08 Jun 2019 12:53:38 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qmma1PwA; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727215AbfFHTxi (ORCPT + 8 others); Sat, 8 Jun 2019 15:53:38 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:45300 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727371AbfFHTxh (ORCPT ); Sat, 8 Jun 2019 15:53:37 -0400 Received: by mail-pf1-f196.google.com with SMTP id s11so3015652pfm.12 for ; Sat, 08 Jun 2019 12:53:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=y4R+1O2JCF2sqyz0/RUxgRqX037Zf7Xz8+zI8QsEWlE=; b=Qmma1PwAldxzd2MM/p3res/Gcc/x5TAFEAC1p/QPRvFRAQm/2TXCS1FgMsS0p+MADA NxYVXKYgitXSUQIrtnBJ2K9hUNnzHvLJoltYx5Xl5v6AmkpPl1sMz834YlszFktEMY29 4WQHnHhnGf20gu6gqDAAx4xhfxUnG63QqdlQ1jD2N5ClNsVmk2pT36ILXXAQ7FzvUfAB yhmSeE+TC275JwCydhX395OMgLyQo783CAxggL+vRclS5ttGwpFwHux0CH8rHTPk92Pb 6r3ZNdbrGQv3gN1dNfvtlIek6Ei+71GWtjeJamvCirAtGQObgTYN5JP3BrqSXEZQ2Xn+ qHtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=y4R+1O2JCF2sqyz0/RUxgRqX037Zf7Xz8+zI8QsEWlE=; b=cIsGmEnnb6qTK+Lqn2feDsRvYM8U6LXrbWMb93rY9b8di8CLQ6P3LdY1oerTCbVQnx 2VeyAhxXSxsWD/ZyTXjsKov8SWCJveqfUHOpS1pZ0VVMawvAsdzpfEMTN/kWKiB0jmIM S5vFwJbsKmBhD+bLXo9e1I+cFE+yxdhgp4MuWRe522moGlIr9jyUTW71f9eNJgSahovU /GwhzGhb2pP+nTcDNHHKkyEgEGmVN6Fo0TUmMBO4Vd5PtCmGSnGBk/dKDJ1Wa1oScWze HXJadG5F9iUJXBhv8jUGIF4uNs0RKBkAuxinR87lKeOOsf6TzYKqNBMF11v4edfsJ+Ik Aaiw== X-Gm-Message-State: APjAAAXHwBa4Rl3eQJpIfkzK+H9cDIgsQSk2jDXbKR3JPGddbjYstf8s EQ+ua18oNk0WuAVyifUOj0KT X-Received: by 2002:a63:1e59:: with SMTP id p25mr8567873pgm.270.1560023616972; Sat, 08 Jun 2019 12:53:36 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7185:fba9:ec1e:ad07:23ac:d3ee]) by smtp.gmail.com with ESMTPSA id b35sm6034377pjc.15.2019.06.08.12.53.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 08 Jun 2019 12:53:35 -0700 (PDT) From: Manivannan Sadhasivam To: ulf.hansson@linaro.org, afaerber@suse.de, robh+dt@kernel.org, sboyd@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, thomas.liau@actions-semi.com, linux-actions@lists.infradead.org, linus.walleij@linaro.org, linux-clk@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH 0/7] Add SD/MMC driver for Actions Semi S900 SoC Date: Sun, 9 Jun 2019 01:23:10 +0530 Message-Id: <20190608195317.6336-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hello, This patchset adds SD/MMC driver for Actions Semi S900 SoC from Owl family SoCs. There are 4 SD/MMC controller present in this SoC but only 2 are enabled currently for Bubblegum96 board to access uSD and onboard eMMC. SDIO support for this driver is not currently implemented. Note: Currently, driver uses 2 completion mechanisms for maintaining the coherency between SDC and DMA interrupts and I know that it is not efficient. Hence, I'd like to hear any suggestions for reimplementing the logic if anyone has. With this driver, this patchset also fixes one clk driver issue and enables the Actions Semi platform in ARM64 defconfig. Thanks, Mani Manivannan Sadhasivam (7): clk: actions: Fix factor clk struct member access dt-bindings: mmc: Add Actions Semi SD/MMC/SDIO controller binding arm64: dts: actions: Add MMC controller support for S900 arm64: dts: actions: Add uSD and eMMC support for Bubblegum96 mmc: Add Actions Semi Owl SoCs SD/MMC driver MAINTAINERS: Add entry for Actions Semi SD/MMC driver and binding arm64: configs: Enable Actions Semi platform in defconfig .../devicetree/bindings/mmc/owl-mmc.txt | 37 + MAINTAINERS | 2 + .../boot/dts/actions/s900-bubblegum-96.dts | 50 ++ arch/arm64/boot/dts/actions/s900.dtsi | 45 ++ arch/arm64/configs/defconfig | 1 + drivers/clk/actions/owl-factor.c | 7 +- drivers/mmc/host/Kconfig | 8 + drivers/mmc/host/Makefile | 1 + drivers/mmc/host/owl-mmc.c | 705 ++++++++++++++++++ 9 files changed, 852 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/mmc/owl-mmc.txt create mode 100644 drivers/mmc/host/owl-mmc.c -- 2.17.1