From patchwork Thu Nov 8 10:44:22 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerome Brunet X-Patchwork-Id: 150494 Delivered-To: patch@linaro.org Received: by 2002:a2e:299d:0:0:0:0:0 with SMTP id p29-v6csp663988ljp; Thu, 8 Nov 2018 02:44:54 -0800 (PST) X-Google-Smtp-Source: AJdET5f10jfYai6MwobMU4nHjHTAe6shKQUXdK15fMDOD3YQpmpOQi/h69Hcxcq1mxkaajdcJjuq X-Received: by 2002:a17:902:bcc4:: with SMTP id o4-v6mr4059403pls.13.1541673894258; Thu, 08 Nov 2018 02:44:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1541673894; cv=none; d=google.com; s=arc-20160816; b=0hTwElgJPdexc3+E98pJU+UmIVZh6SSVNr7FTch8JHybeEz4Sigfd1l2NctMsjdP7R 4i9kbdgbZw0iHSCNaITKl5Spo4tn+e/Dl9AIj3jYH2ix16tq8/9etVKvNJO3kDRyqUAD jbIO+qEritxb6QdcFWxBHcL5tJu9jpHSM3pKpjHIEvhEwJnzHBM7k63MwkiKyf50zb+y CYj+eFujORR3pGfGBcw4bwGqCmlS+DMNJK/Y4g9jkYimnhN7A4CLhO3dZhoGv3/+mQs6 Avxo45b+QVSz4GPfAQpl/5AGXxwepchYIq6RNOzO9oouYsss/J9xnADBU9WeTu11G8KJ cyUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=vhPNVmfRa7pNj+I7+aRTRJyzPUhJcyunyJ631PKqVN0=; b=z/fhVSPU8yPWcaML13iLiCzrrJq6z8YHa5tD3C4iZspS1qQ0Ur+EI/Z2SB9EqCFGqs Fd+74b0UeHYbZbhfP069I7r9qwoztWb24yuq4IWT/QJrH6/lsoPoy5GZ3eS/j3hpSdEJ ZKDYj6vtaWTQj7AKI5/JO4F6vsOcJih+1YBksSurf5zS6GA+I1Cm9xt6VXtjjkYP2w4Y gZND6DzTvT8hFq3FW2EouIaF7l13poSqd5rdrM1X269izxFSCVtWeLIVw73/USyL4IHG 4AdrtUlRunc5UObL6f6bvb1QnjA8GT5DuclIilqIjfe+PihRYEUdQ6QMb39/0WEbHdD4 q4rA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=KAuDRxfV; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id o13-v6si4358780pfd.46.2018.11.08.02.44.54; Thu, 08 Nov 2018 02:44:54 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20150623.gappssmtp.com header.s=20150623 header.b=KAuDRxfV; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726883AbeKHUTn (ORCPT + 6 others); Thu, 8 Nov 2018 15:19:43 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:53678 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726304AbeKHUTn (ORCPT ); Thu, 8 Nov 2018 15:19:43 -0500 Received: by mail-wm1-f67.google.com with SMTP id f10-v6so749022wme.3 for ; Thu, 08 Nov 2018 02:44:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=vhPNVmfRa7pNj+I7+aRTRJyzPUhJcyunyJ631PKqVN0=; b=KAuDRxfV51gyqH2rydf36nfkogw6aaFx9BalBn1zZaWDQCAWu3nPiQZHmSWC9i7CsS LU/i8c+wmoYJ4s1jDGJiZMeurcXyb/56EmgGoBMdhofORAmcrdu86yd3U2Wzg9+OCWGn iT/IdNpg/nMGMlllh706QcbIjc8lUEseB92YGm+QWGKY+PbTY7+sANcfGFirqOV6IOct +gkrV2feHpoun1ip/T6Wu5+PqUP5JrqqbPWtlAL5rbRijy93TofjQT+2VL/L4BSkPwuJ rvEhFV7BA0yq9KAI1Ay665ZG/XPoVrvoay3JQtafh7MpBU9ox4kCG2yLfO2qbEfevHq2 Qq5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=vhPNVmfRa7pNj+I7+aRTRJyzPUhJcyunyJ631PKqVN0=; b=dIjJHPvLCZOiCJwkKyabAs2Ltip2k0IOPzVL1LrTj9Te2OBw1smv1dBxDdSw580ji3 aBjpHjCp+U6uxLZagyy+GKrJg9x4XgsYGe7Njmnczam/dYMTjKtHbJFPaBc9GuDSL/K5 ZLuHtHfvImMCqzh6yafmRxhjA/jBI6YrNKct+6gRb2ET4mZPP8OASp6D6M50I1y5K+5/ VMEqJpaCKgv0+qLZgOY3GkKUAZGyBtBJedx/Mdf7ZyXbeL8US0jxZVyEnbbcTr6QgI/6 vVUKwZtb2TYV2A9mE1w/8Fk6jnhDDTCduMuQamWMObQuyMeepgj0Pl9zXpIUYsn9P8HZ 4CXw== X-Gm-Message-State: AGRZ1gKoh6OjTbVB0Z3dnranbPpuW3BaWCxwT3oToRYxcv1lvkw14Sgj JgQ0F0BEfvi2n6Bwk8R4PXf90H7MU2U= X-Received: by 2002:a1c:38c1:: with SMTP id f184-v6mr780517wma.24.1541673889832; Thu, 08 Nov 2018 02:44:49 -0800 (PST) Received: from boomer.local ([90.63.244.31]) by smtp.googlemail.com with ESMTPSA id o130-v6sm5884800wmd.11.2018.11.08.02.44.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Nov 2018 02:44:49 -0800 (PST) From: Jerome Brunet To: Kevin Hilman , Carlo Caione Cc: Jerome Brunet , devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/4] ARM: dts: meson: set pinmux bias Date: Thu, 8 Nov 2018 11:44:22 +0100 Message-Id: <20181108104426.1877-1-jbrunet@baylibre.com> X-Mailer: git-send-email 2.19.1 MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Amlogic chipsets, the bias set through pinconf applies to the pad itself, not only the GPIO function. This means that even when we change the function of the pad from GPIO to anything else, the bias previously set still applies. While trying to boot from SPI, I noticed the eMMC was not working anymore. Even if the related eMMC pad are not used by the SPI, the ROM code sets a pull-down on the eMMC pad and leaves it that way. This breaks the eMMC later on, in both u-boot and Linux. The underlying issue is that we inherit whatever was left by previous user of the pad (pinconf, u-boot or the ROM code). As a consequence, the actual setup we get is undefined. There is nothing mentioned in the documentation about pad bias and pinmux function, however leaving it undefined is not an option. This patchset consistently disable the pad bias for every pinmux functions. It seems to work well, we can only assume that the necessary bias (if any) is already provided by the pin function itself. I can't really test every pinmux configuration and it is fairly possible I missed something so it would be nice if more people could confirm if nothing (new) is broken after applying this series. One things could be the i2c. Usually the i2c pull-ups are physically present on the board but, if they are missing on platform, we may define a special pinmux setting with pull-up enabled. One last gotcha, I recently posted fixups around bias setting to pinctrl which have been merged: [0] [1]. These must be applied before applying this series, otherwise when requesting 'bias-disable' you'll probably get a pull-down instead. [0]: https://lkml.kernel.org/r/20181023160319.27003-1-jbrunet@baylibre.com [1]: https://lkml.kernel.org/r/20181029151340.9087-1-jbrunet@baylibre.com Jerome Brunet (4): arm64: dts: meson: remove extra subnode in mmc clk_gate pinmux arm64: dts: meson: disable pad bias for mmc pinmuxes arm64: dts: meson: consistently disable pin bias ARM: dts: meson: consistently disable pin bias arch/arm/boot/dts/meson8.dtsi | 12 +++ arch/arm/boot/dts/meson8b.dtsi | 9 ++ arch/arm/boot/dts/meson8m2.dtsi | 1 + arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 111 ++++++++++++++++++-- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 60 +++++++++-- arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 62 +++++++++-- 6 files changed, 231 insertions(+), 24 deletions(-) -- 2.19.1