From patchwork Fri Jul 27 18:45:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 143086 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp1166602ljj; Fri, 27 Jul 2018 11:46:42 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfpU10bxvDyqhB0PPejgYxx3oh9igaifThzro2scWTzr5IgHrdFd8Cc3PKa+Blzi6mJVMao X-Received: by 2002:a62:3703:: with SMTP id e3-v6mr7828652pfa.117.1532717202451; Fri, 27 Jul 2018 11:46:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1532717202; cv=none; d=google.com; s=arc-20160816; b=XnM9us1Zk5oA0grj1QHjsWBQx9Mo5fMQYQAPxJWpAqXB0xaWCOUSnXAsRlO/agbuYE 2zniQN745TtjRAja+PiljAP6VN9VmovrJASwRPYHjMx9ajFQcSW4VISV5P+ZNZt82OQx q0ID6WYmR5ahzZo69YzrMgnjW1MCVHYDkalZe6JvQq3WSg5so9DOkPwS8x154kFEKF8H LIsJgBEAs1VY5AcPwYszdsIYBGjbsWFBaHxXDpfPyGDKO9MTsJ2ZcrW8ZfL05s40KGMe bTa1dNC+omrTIvl2ysup6Ci+Iq/VgTxjm1VgUKAlyUamg86EBjGsksZjnXS7CrOkGJAl 5cvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=OiuqKluF7wGDs2+c2fOXp5+Xt0Gc1TklSROmIYdQ0/U=; b=S6ktcDXnkoUsydqc53cva+Y2A+6NowlEx0XNNiUL0YEyRqqZ9bd6YBDiMuB4uvHTxT iC513gfvE2Uelip3T0uYyJrvUbtqcOCcA/PsSGePpQ25k2HkMPdydy/AWiC9a3VyuxnD maxmshmoh8hgLIz8LaMaGdeZFE0gTR+yjDjkNkwVVHjqwyjx2K6npoZbbTCvBBLarZ6w ZTmn8m+o++f1Ni+cp05W4RyQk8T76Fjc5kvKIIvm6dpayhzYNzHRXXJvYN4/+8xVC9Vp Nl/c+ATCOSN7oMPfQ35mvGk0LvC3dRggS8RGoUQg0vS9tGarSJ/ES9lkDaW2GwndCqO0 M+HA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=bzOvJIGA; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j20-v6si4184365pgb.92.2018.07.27.11.46.42; Fri, 27 Jul 2018 11:46:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=bzOvJIGA; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388982AbeG0UJu (ORCPT + 5 others); Fri, 27 Jul 2018 16:09:50 -0400 Received: from mail-pf1-f194.google.com ([209.85.210.194]:45689 "EHLO mail-pf1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388964AbeG0UJu (ORCPT ); Fri, 27 Jul 2018 16:09:50 -0400 Received: by mail-pf1-f194.google.com with SMTP id i26-v6so2019326pfo.12 for ; Fri, 27 Jul 2018 11:46:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=5FC7TeMTQ3IsSPp6n95qC1z3uRHEWTZfinsf63P4O1M=; b=bzOvJIGAnprqFhC1zXSb1t7zBx7rAhg7wet88rwu5nppb6ySgUxxxdLg8Juuxf4CSV p0ny5CeY2+4BJWhVEmDYeLaCUzR4s7RGVd4amNtnXa+GZ7dREpDKN92w7sNrwb+/gHx2 M1a2ilw4j7TCzF3qk//5uYjLWmxj3xqaW41GE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=5FC7TeMTQ3IsSPp6n95qC1z3uRHEWTZfinsf63P4O1M=; b=FV0mP9rSVTNbEs/tl6fxUCmsFWPjUpvfT9eNE7Fuo152EBGbEww+368LqZwY9+nl3c fUTAA70UjwltH6p5AaxZ1OrFCSGSQokvvn6nF7rYkwsoaBdC7VDQFEyt+IqjdYbvfzC1 OfJIbbm9Ru+yakKSqumDV+U+kBN7Q5HgtU50fknMMu1pYmqMEV2EKlL1WG4souG7YAwR tjUp9We9rrI3BYL11SnTxX8cGSdhoeWv2l8YvQlZa88h03Iy+Sh+hrPytI1HthLB91eE 4YB5OK7OkjEYi3dhGLusJ4MD9oiC0Tzr8zpBrYfHM13ZHClKRwQhkHGX4j6IQUFFs2Un BTtg== X-Gm-Message-State: AOUpUlEjUmIimDbFhDRerk5i/T1BLvaOvfuPSRd+CoI4ysJf/8o1Wrwu cXsBLX0jQS4ACniNG+x9OZd3 X-Received: by 2002:a63:a347:: with SMTP id v7-v6mr6999456pgn.182.1532717200874; Fri, 27 Jul 2018 11:46:40 -0700 (PDT) Received: from localhost.localdomain ([2405:204:7308:c330:41b:cc59:b463:ec7b]) by smtp.gmail.com with ESMTPSA id t69-v6sm13817959pfj.7.2018.07.27.11.46.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jul 2018 11:46:40 -0700 (PDT) From: Manivannan Sadhasivam To: p.zabel@pengutronix.de, mturquette@baylibre.com, sboyd@kernel.org, afaerber@suse.de, robh+dt@kernel.org Cc: linux-clk@vger.kernel.org, liuwei@actions-semi.com, mp-cs@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, pn@denx.de, edgar.righi@lsitec.org.br, sravanhome@gmail.com, Manivannan Sadhasivam Subject: [PATCH 0/9] Add Reset Controller support for Actions Semi Owl SoCs Date: Sat, 28 Jul 2018 00:15:18 +0530 Message-Id: <20180727184527.13287-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patchset adds Reset Controller (RMU) support for Actions Semi Owl SoCs, S900 and S700. For the Owl SoCs, RMU has been integrated into the clock subsystem in hardware. Hence, in software we integrate RMU support into common clock driver inorder to maintain compatibility. This patch series depends on the recently posted S700 clk series: "[PATCH v7 0/5] Add clock driver for Actions S700 SoC". For the S700 clk series, driver and bindings patches are applied through the clk tree. But the DTS patches are not yet picked up by the platform maintainer, Andreas. Hence, Andreas is expected to pick the DTS patches in this series once reviewed by the maintainers along with S700 clk DTS patches. Because of the absence of the S500 SoC clk support, the reset controller registration code is added to both S700 and S900 SoC clk drivers for now. But once S500 clk support is added, the reset controller registration part will be moved to Owl SoCs common clk code. Thanks, Mani Manivannan Sadhasivam (9): clk: actions: Cache regmap info in private clock descriptor dt-bindings: clock: Add reset controller bindings for Actions Semi Owl SoCs dt-bindings: reset: Add binding constants for Actions Semi S700 RMU dt-bindings: reset: Add binding constants for Actions Semi S900 RMU arm64: dts: actions: Add Reset Controller support for S700 SoC arm64: dts: actions: Add Reset Controller support for S900 SoC clk: actions: Add Actions Semi Owl SoCs Reset Management Unit support clk: actions: Add Actions Semi S700 SoC Reset Management Unit support clk: actions: Add Actions Semi S900 SoC Reset Management Unit support .../bindings/clock/actions,owl-cmu.txt | 2 + arch/arm64/boot/dts/actions/s700.dtsi | 2 + arch/arm64/boot/dts/actions/s900.dtsi | 2 + drivers/clk/actions/Kconfig | 1 + drivers/clk/actions/Makefile | 1 + drivers/clk/actions/owl-common.c | 3 +- drivers/clk/actions/owl-common.h | 5 +- drivers/clk/actions/owl-reset.c | 72 ++++++++++++++++ drivers/clk/actions/owl-reset.h | 32 +++++++ drivers/clk/actions/owl-s700.c | 55 +++++++++++- drivers/clk/actions/owl-s900.c | 86 ++++++++++++++++++- .../dt-bindings/reset/actions,s700-reset.h | 34 ++++++++ .../dt-bindings/reset/actions,s900-reset.h | 65 ++++++++++++++ 13 files changed, 354 insertions(+), 6 deletions(-) create mode 100644 drivers/clk/actions/owl-reset.c create mode 100644 drivers/clk/actions/owl-reset.h create mode 100644 include/dt-bindings/reset/actions,s700-reset.h create mode 100644 include/dt-bindings/reset/actions,s900-reset.h -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html