From patchwork Wed Jul 18 20:07:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 142296 Delivered-To: patch@linaro.org Received: by 2002:a2e:9754:0:0:0:0:0 with SMTP id f20-v6csp944687ljj; Wed, 18 Jul 2018 13:08:48 -0700 (PDT) X-Google-Smtp-Source: AAOMgpfAOznBXz2lFpTMIFlGJb0HJF9QOlxYPLiUjWuhsgz8f+L8yjv/g6ZdAU1xxrek2F3fpQG7 X-Received: by 2002:a17:902:ac96:: with SMTP id h22-v6mr7291913plr.17.1531944528585; Wed, 18 Jul 2018 13:08:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1531944528; cv=none; d=google.com; s=arc-20160816; b=m/RFiaOostbiFJEEee1xoG2od3sOpUUixAv6+q/9p6St2rH6z/K1FM9yJn2pA7w+WT NXsHWlhpHYActZAX50nqE2y790ToRuVNzOGLSDBBYd0VcPYYibJRFiJDlkum9G3MxXeX v3TkgYDDrxXA/sRYK6ZV5Lgns/991rCLSYxSMp/F5hYu0dNdr9Fi0UbxSlSuroiTJqaa 0F/VY1K5bMcIE2ZZvr3HCHep7W3N6427qjrEAxIwKPqWyWXA8BzG4z5cUJak/oJG4Xxg 8chROjc+iUeKtFkqVYaGnLaxW4qnlXolqjUl8CrS+o9luJtNdKbhl9mOQ5QZo3CNXRfM 0iNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=f/xArJCEuykAk1zR+/Nw3UfRqS87SLQEsqlfhp+6W8M=; b=asp7NEZGESMU8SLWg6t+pZIAVV/k0puf60gj+9MG8ENvmcd6u85nXNLo0U1UKv3PQK uFm0VNVpoYR1uykxHjwx0fWrvIpu6YTFCPwS/0rOHgDjb9gQMM3Kp8zswecF5BgBuVnZ 5EmCcjGgWJ977cjWtUDcgWIXFpE0N1TftmeMNmKs2eF4Cbp7B/ADeBRzG0LTK0CzasCj lrvDAvhzYNvhtX6Sd97n3RU6dezbJ9mhSvwkoyj0mLLfMLXywt/ZTneh6W4WmKNynaXO Bqz+t9NMBAAgsc1qpPupUtLAQXQmvENQgCQHXjl/+0CEw/GHo7r13ugIHAU94ChvasAS Kr0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=cOjR1Lve; spf=pass (google.com: best guess record for domain of dmaengine-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=dmaengine-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bd3-v6si3780422plb.171.2018.07.18.13.08.48; Wed, 18 Jul 2018 13:08:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dmaengine-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=cOjR1Lve; spf=pass (google.com: best guess record for domain of dmaengine-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=dmaengine-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730348AbeGRUsQ (ORCPT + 3 others); Wed, 18 Jul 2018 16:48:16 -0400 Received: from mail-pl0-f67.google.com ([209.85.160.67]:33746 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729702AbeGRUsQ (ORCPT ); Wed, 18 Jul 2018 16:48:16 -0400 Received: by mail-pl0-f67.google.com with SMTP id 6-v6so2526107plb.0 for ; Wed, 18 Jul 2018 13:08:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=wIr4kNwoFEqSdaZpIdHL68f83dzsEGLYfaM+xhxAnLM=; b=cOjR1Lve5uMr1pui3luHzDatDM6q21SWmV79THswBwr0wP+wir60+JJ7pOL+pgJBPm Hcqu1HQpEufPKDNMVG3eIjUEjSDKY6uZmrpwwUG2rhuYgEPpiWqqAbagV3RYdHQ+qGic Ks0qvE1HRvhRpP8zPYnwKrHEPe2h1ezR2nyN8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=wIr4kNwoFEqSdaZpIdHL68f83dzsEGLYfaM+xhxAnLM=; b=J22h2P8FapvdiNOaPWNOJdei8vAg53iSCCN9Y0OHeqnbgINxzN0USjo/F1ceCdkkBO 6XNd9QdGWYq2ks2gzA9V17QngKqdnCtfLSWgNUXNYDkgKi7XRrnGvAHUs+F4w5DdLeqn WsHilQcxeXyzBgq3SBv/HJvqFS8V0gcxFGjchsv3FLX7OUs7g1h6Oaa2XM+71IPA+sRb NjOajvy1ySB4WCgaDTa6pnGavICrc2NXvj3A0/+KNkqq5D2SCeKs5r3eYV+k+lx89j3J haK1y4dYyrQ9oL4AzGs0HRWRNOG/mqqCAdxsHacBUS+zQbo8GwBG0eS0yVRCL2j+vh6B +HyA== X-Gm-Message-State: AOUpUlGzhziXpzb98ZvEkzcEXSeLKgTFBTxzsR/NrQJpkQpFLPcInt+3 yOZXNLeZQXUsYS6fOH4hQ95zgrGWlA== X-Received: by 2002:a17:902:74c2:: with SMTP id f2-v6mr7156345plt.260.1531944527157; Wed, 18 Jul 2018 13:08:47 -0700 (PDT) Received: from localhost.localdomain ([2409:4072:628d:5c0b:b467:58cc:4c91:39b3]) by smtp.gmail.com with ESMTPSA id c7-v6sm6924697pfh.25.2018.07.18.13.08.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 18 Jul 2018 13:08:46 -0700 (PDT) From: Manivannan Sadhasivam To: vkoul@kernel.org, dan.j.williams@intel.com, afaerber@suse.de, robh+dt@kernel.org Cc: dmaengine@vger.kernel.org, liuwei@actions-semi.com, 96boards@ucrobotics.com, devicetree@vger.kernel.org, daniel.thompson@linaro.org, amit.kucheria@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, hzhang@ucrobotics.com, bdong@ucrobotics.com, manivannanece23@gmail.com, thomas.liau@actions-semi.com, jeff.chen@actions-semi.com, pn@denx.de, edgar.righi@lsitec.org.br, Manivannan Sadhasivam Subject: [PATCH 0/4] Add Actions Semi Owl family S900 DMA Controller support Date: Thu, 19 Jul 2018 01:37:05 +0530 Message-Id: <20180718200709.27102-1-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.17.1 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org This patchset adds DMA controller support for Actions Semi Owl family S900 SoC. This driver has been structured in a way such that there will be only one controller driver for the whole Owl family series (S500, S700 and S900 SoCs). There are 12 physical channels and 46 logical channels supported by the DMA controller. The DMA controller also supports 4 software configurable interrupt lines for the priority based DMA usecase. But the DMA driver supports only 1 interrupt for simplification. By default, the driver uses Linked list mode for all transfers. Right now only MEMCPY support has been added and the rest (SLAVE, CYCLIC) will be added in upcoming patches. The driver has been tested using dmatest utility on the Bubblegum-96 board. The DTS patches in this series depends on the pinctrl DTS patches submitted [1], which is yet to be merged by the platform maintainer Andreas. Since the DMA driver goes through DMA tree and the relevant DTS patches goes through ARM-SoC tree, Andreas will pick it up once it has been reviewed. For the reference, I have queued up all reviewed dts patches so far in my repo [2] from which Andreas is picking them for 4.19. Thanks, Mani [1] https://patchwork.kernel.org/patch/10322937/ [2] https://git.linaro.org/people/manivannan.sadhasivam/linux.git/log/?h=s900-for-next Manivannan Sadhasivam (4): dt-bindings: dma: Add binding for Actions Semi Owl SoCs arm64: dts: actions: Add Actions Semi S900 DMA Controller dma: Add Actions Semi Owl family S900 DMA driver MAINTAINERS: Add entry for Actions Semi Owl SoCs DMA driver .../devicetree/bindings/dma/owl-dma.txt | 46 + MAINTAINERS | 2 + arch/arm64/boot/dts/actions/s900.dtsi | 13 + drivers/dma/Kconfig | 8 + drivers/dma/Makefile | 1 + drivers/dma/owl-dma.c | 1021 +++++++++++++++++ 6 files changed, 1091 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/owl-dma.txt create mode 100644 drivers/dma/owl-dma.c -- 2.17.1 -- To unsubscribe from this list: send the line "unsubscribe dmaengine" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html