From patchwork Thu Nov 2 03:53:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 117741 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp1665608qgn; Wed, 1 Nov 2017 20:54:05 -0700 (PDT) X-Google-Smtp-Source: ABhQp+Sa+f7ETTNQjrWthiSQB8cU8dG5Z3umrCIKNNkk9gXy94bzcdyxKGK7wiAb9PzDUkJMrnYg X-Received: by 10.101.96.68 with SMTP id b4mr2055957pgv.155.1509594844942; Wed, 01 Nov 2017 20:54:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509594844; cv=none; d=google.com; s=arc-20160816; b=rlLmf2AbcijUR0LxQRRF2aXxZPvv/7a4TQzhoLRYOnXO8pLyDmN5oV5yfC4oD4GKR+ 5xtJJNUDUwtJCJWR0Me2s6KUBUpYZVNCSX9Zf0nDvTQ9tN3CC1Xwf2OwQlFYu6ekycP6 cOOvQbUWlU2EUssCwjrwUVSSPFDs7BJpzjl9MrmueaLYJxAopjjRU0ldYxPlQXwYWVch fzlXoEnESn3ack4tHi31p+Pk3nlP6NWeRd+aHOYXV0AvoZgsHmD5jonWVUsIAx+Wpj7x ynO3BYBRQmb7pRjzAUcGab9U1GO07iWkSbIc59V1qkNp8M1JAAds0VtrPi/zG+n1dDry 3x7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=j6yk9LUY0VUG1iJG2ttgu1KVxGLGvD6qAcPVdLOJH8E=; b=HlEZl/AKdXxhPtkUFBZnwZFORbsvx39e6HBZBtGm9N2JIF4QdoJl1/9EbRTGz+cNtB PnhrBUz5gVjfil8teI3BjXIxhBFVkDzzCSaquHFo99W8ZVVGPdxVS+DJViREu6oSUIc+ vGNIIxMbPSIb5n4P2BNjtgMJ/a6e3GJVTO0OGPUsbzoR7enWuQc5798MvsrI5GVhs33j 5Ou9/LDMa5WjP8zOlhjKHE5eiisEKpqJe9tWn/PbWIRxs80LtfaytEyC0NUVkCWyBHBo Fqn3o39xw/KqDbkHY2pa32jedu9ByUPESI1t9qRtZmAjMJwOCRBWYVUXpURokvrdJzoY jVZg== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@gmail.com header.s=20161025 header.b=kaNW1snh; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a92si1156927pla.28.2017.11.01.20.54.04; Wed, 01 Nov 2017 20:54:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@gmail.com header.s=20161025 header.b=kaNW1snh; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934099AbdKBDyD (ORCPT + 6 others); Wed, 1 Nov 2017 23:54:03 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:51388 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934073AbdKBDyC (ORCPT ); Wed, 1 Nov 2017 23:54:02 -0400 Received: by mail-pf0-f195.google.com with SMTP id n14so3588496pfh.8; Wed, 01 Nov 2017 20:54:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=LK2so7/2ZPecEWMb+oP1+JVUs+YF//8HiWZ7Gr/ANrk=; b=kaNW1snhIWXiqdPaMBQXCzFmcc+/HsQil8OwAfxn3gjMf/Amuvfnt7NMM5yF3fdsry 8dMBXXQ0C99OHGVa8mGIsMhfD5GQ/u5azuJNT7AKRcTLsDEPDZj/lPmrsYthOEIpYzaC hjXxk9BGJNsOpHvc1K1JaSxy6sDkCchwhQotd2XymJYommYylyGaKurCqyOVcR1WJyJP bcYXDmOsI7CDnYAweeHh0Psv/h/azbRvi/p5Pi0nGYDHkeV11osZGHVlF0Aj+7ziJRVB GPdO2/sGzSa5740Khr9l7C5zuLDFzcbnqAqCn/igMDmEQH2YGmCUFHdYv3Rx9YXd3NeI 2XhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=LK2so7/2ZPecEWMb+oP1+JVUs+YF//8HiWZ7Gr/ANrk=; b=X17r+o3ww5s0P4wW+1dYwmapvR/glf495lbuTFoyosrIwYjPLd2CpbaFzGb5Wbo8wO Q0204Vz1BxwLgb2MTl4wFWMKhbuFLkKxGJkAXaTcQH+f5aaJEfktBTMs7N6k7EVgU7U8 3TleLk53k1+MidV5sVWqF9aE0s1m8ZmOrP9v44rVCjFT8K7rillmZqg0l5jwb0GspHrk pMSGghj1yBD7/zuLrP/pB0PtBdqOWG3WZ6bkpHADNZfc8EwzHH+q7ooF4KhlAZAyq0PS +fpyoShrUDT3pCQzKNll8tn9f3R3aBx/NUN4LnIGX5J0qDQ4/DV+8+oTaoVEvp8W+PrO df1A== X-Gm-Message-State: AMCzsaUNiXDlCwuQAMkJNJWka+D/Ng2dvL0sziWIZ+PswSNO5rnU5y0S eYKMhFbv6+B3qnB/4S7gI0Q= X-Received: by 10.84.240.135 with SMTP id z7mr1819373plk.445.1509594841420; Wed, 01 Nov 2017 20:54:01 -0700 (PDT) Received: from aurora.jms.id.au ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id l5sm3984177pfi.165.2017.11.01.20.53.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 01 Nov 2017 20:54:00 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 02 Nov 2017 14:53:52 +1100 From: Joel Stanley To: Guenter Roeck , Rob Herring Cc: Philipp Zabel , Mykola Kostenok , Jaghathiswari Rankappagounder Natarajan , Patrick Venture , Andrew Jeffery , devicetree@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/3] hwmon: Add reset support to aspeed-pwm-tach Date: Thu, 2 Nov 2017 14:53:46 +1100 Message-Id: <20171102035349.1902-1-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Gunter, This adds reset controller support to the ASPEED pwm/tach driver. The reset controller and clock driver is currently under review, so to test those patches must be merged in to fully test these changes[1]. To address your concerns from v1: This driver was not usable as-is upstream. I believe the developer(s) tested and deployed it in the OpenBMC kernel tree which has some hacks in mach-aspeed to release all of the resets. The other way they could have tested it is by booting an OpenBMC kernel, which releases the resets, and then testing the upstream kernel without performing a power cycle as the resets are not reasserted on reboot. I realise it is not ideal to be changing already merged bindings. I don't plan on it becoming a habit. There is no BIOS or other ROM that runs before Linux on a BMC to release the resets. We do have u-boot, but that does not modify the pwm reset. I haven't added a Kconfig dependency on the RESET_CONTROLLER as the driver can build without it, and when the ASPEED clk/reset driver is merged, the platform will always have that option selected. I've given this version a day of testing on hardware I have access to. [1] https://lwn.net/Articles/737697/ Joel Stanley (3): hwmon: (aspeed-pwm-tacho) Sort headers hwmon: (aspeed-pwm-tacho) Deassert reset in probe dt-bindings: hwmon: aspeed-pwm-tacho: Add reset node .../devicetree/bindings/hwmon/aspeed-pwm-tacho.txt | 14 ++++------- drivers/hwmon/aspeed-pwm-tacho.c | 27 +++++++++++++++++++--- 2 files changed, 29 insertions(+), 12 deletions(-) -- 2.14.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring