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[209.132.180.67]) by mx.google.com with ESMTP id i72si6128715pfe.165.2017.10.17.09.56.07; Tue, 17 Oct 2017 09:56:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=XFnyMGci; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934133AbdJQQ4G (ORCPT + 6 others); Tue, 17 Oct 2017 12:56:06 -0400 Received: from mail-wr0-f173.google.com ([209.85.128.173]:45257 "EHLO mail-wr0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934082AbdJQQ4F (ORCPT ); Tue, 17 Oct 2017 12:56:05 -0400 Received: by mail-wr0-f173.google.com with SMTP id k7so2393370wre.2 for ; Tue, 17 Oct 2017 09:56:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=j/JF9XN1x0ujVALqeG9TIVvJqkrB6PUr635G/gF4wkA=; b=XFnyMGciVpbsRbJLhpExGRoFij138HexY9zol7+im/6pm2IpoqtVuM4UZwF832cj5b BIEaxQLmEZXSKAO7nywvXLpVc1INP1jJ1lNJyNzAFlRW5brxYB31Pt6zymlGMsIhVp7X +ynl1iLsvvJyTwUIAKD6RDXZ7J14RztPBPsEg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=j/JF9XN1x0ujVALqeG9TIVvJqkrB6PUr635G/gF4wkA=; b=fe4gBND4TUP88kXC2c7k4pYg+7y4RHXyXuOSYwEteIXb7VeKI85YS+mf/e6t2for5f OXeyssbViC3fAtrUl29H1V8ob5MHKi4awttAddx144XWUTW4iEKqMIuBmyoq9J+FIbyh LZC+DmAuDz/jlkxMsADRBrgjZf/kH4tSd9tXIakLrB+4XFJwlGwmKp7gSD94U8I83q0i WtpCly4V+I44zPVI8POgwTO6edqK9d1Y+G9yrDLuHag5KkKh2IVYkiYPA1+iKMHqaXli iLfesJr+x6s6ZmXrchXm5E7uNirFIGxJOFoTJFnmETNLU8BmnNYlOMQJA9wDlPldPTaT 8VNA== X-Gm-Message-State: AMCzsaXcMiXOU1wVXVQxTgC3sGqNFlpwCIOHeY/vHXYonX070A9cZ1Gb pueAh+SGTPENEo1nYMf96nlxxA== X-Google-Smtp-Source: ABhQp+Rx4QE3bZtMsk6Hh+vCbAVzYrC4uMg9uxWLP9NeXsxCKtpOW2Fnxsc7Mvs2H4PBgqh7eV5fEA== X-Received: by 10.223.160.247 with SMTP id n52mr4146088wrn.260.1508259364052; Tue, 17 Oct 2017 09:56:04 -0700 (PDT) Received: from localhost.localdomain ([154.144.50.139]) by smtp.gmail.com with ESMTPSA id y84sm5854517wmg.43.2017.10.17.09.56.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 17 Oct 2017 09:56:02 -0700 (PDT) From: Ard Biesheuvel To: marc.zyngier@arm.com, robin.murphy@arm.com Cc: linux-arm-kernel@lists.infradead.org, daniel.thompson@Linaro.org, leif.lindholm@linaro.org, graeme.gregory@linaro.org, catalin.marinas@arm.com, will.deacon@arm.com, devicetree@vger.kernel.org, robh+dt@kernel.org, Ard Biesheuvel Subject: [PATCH v5 0/3] implement workaround for Socionext Synquacer pre-ITS Date: Tue, 17 Oct 2017 17:55:53 +0100 Message-Id: <20171017165556.30250-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org >From patch 3/3: The Socionext Synquacer SoC's implementation of GICv3 has a so-called 'pre-ITS', which maps 32-bit writes targeted at a separate window of size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device ID taken from bits [device_id_bits + 1:2] of the window offset. Writes that target GITS_TRANSLATER directly are reported as originating from device ID #0. So add a workaround for this. Given that this breaks isolation, clear the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well. v5: - move back to using a single DT property to describe the window; this is appropriate given that the CPU never accesses the window, and so modelling it using the standard DT idiom involving buses and ranges is not necessary v4: - add patch to allow the quirk hook to signal whether it was applied or not; this is necessary for hardware whose IIDR is not sufficient to identify it - use DT sub-node rather than property to describe the quirk - remove pre_its_size field, and use get_msi_base() function pointer instead v3: - add patch to pull device ID space discovery forward, so we can quirk it as well (as we already do for Cavium) - use existing quirks framework as much as possible - get rid of ITS_WORKAROUND_xxx flag: it is no longer needed after the refactoring v2: - use a 32-bit host address/size rather than a PCI address, to factor out the involvement of an SMMU (which the platform does have, but it is unclear atm if it can be exposed to the OS) - add msi_domain_flags member to move the quirk flag checks out of the common code path* Ard Biesheuvel (3): drivers/irqchip: gicv3: probe device ID space before quirks handling drivers/irqchip: gic: make quirks matching conditional on init return value drivers/irqchip: gicv3: add workaround for Synquacer pre-ITS Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 4 + arch/arm64/Kconfig | 8 ++ drivers/irqchip/irq-gic-common.c | 5 +- drivers/irqchip/irq-gic-common.h | 2 +- drivers/irqchip/irq-gic-v3-its.c | 102 ++++++++++++++++---- 5 files changed, 101 insertions(+), 20 deletions(-) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html