| Message ID | 20170928075149.8154-1-joel@jms.id.au |
|---|---|
| Headers | show |
| Series | ARM: dts: aspeed: Device tree updates | expand |
On Thu, Sep 28, 2017 at 12:51 AM, Joel Stanley <joel@jms.id.au> wrote: > Enable the buses that are in use and the devices that are attached. > Currently that includes temperature measurement and EEPROM. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Brendan Higgins <brendanhiggins@google.com> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, 2017-09-28 at 17:21 +0930, Joel Stanley wrote: > > From: Andrew Jeffery <andrew@aj.id.au> > > Moving the subnodes out of the pinctrl node declaration to a reference > allows easier access to the remaining parts of the devicetree. > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > Reviewed-by: Xo Wang <xow@google.com> > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > arch/arm/boot/dts/aspeed-g4.dtsi | 1483 ++++++++++++++++++------------------ > arch/arm/boot/dts/aspeed-g5.dtsi | 1549 +++++++++++++++++++------------------- > 2 files changed, 1518 insertions(+), 1514 deletions(-) I hate the way the diff came out for the g5, it's almost impossible to read. Also not sure how useful it is to ack my own patch, but given the rebasing it has suffered: Acked-by: Andrew Jeffery <andrew@aj.id.au> Cheers, Andrew
On Thu, 2017-09-28 at 17:21 +0930, Joel Stanley wrote: > We try to keep the nodes in address order. The ADC node was out of > place. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > arch/arm/boot/dts/aspeed-g4.dtsi | 16 ++++++++-------- > arch/arm/boot/dts/aspeed-g5.dtsi | 16 ++++++++-------- > 2 files changed, 16 insertions(+), 16 deletions(-) > > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi > index 1edd0cee6221..a4579498fc25 100644 > --- a/arch/arm/boot/dts/aspeed-g4.dtsi > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi > @@ -129,6 +129,14 @@ > }; > }; > > + adc: adc@1e6e9000 { > + compatible = "aspeed,ast2400-adc"; > + reg = <0x1e6e9000 0xb0>; > + clocks = <&syscon ASPEED_CLK_APB>; We can't do this yet as the clk driver isn't yet merged, and it breaks from the "just move the node" description in the commit message. > + #io-channel-cells = <1>; > + status = "disabled"; > + }; > + > sram@1e720000 { > compatible = "mmio-sram"; > reg = <0x1e720000 0x8000>; // 32K > @@ -227,14 +235,6 @@ > no-loopback-test; > status = "disabled"; > }; > - > - adc: adc@1e6e9000 { > - compatible = "aspeed,ast2400-adc"; > - reg = <0x1e6e9000 0xb0>; > - clocks = <&clk_apb>; > - #io-channel-cells = <1>; > - status = "disabled"; > - }; > }; > }; > }; > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi > index f56dd67efa50..f6430b313f90 100644 > --- a/arch/arm/boot/dts/aspeed-g5.dtsi > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi > @@ -173,6 +173,14 @@ > reg-io-width = <4>; > }; > > + adc: adc@1e6e9000 { > + compatible = "aspeed,ast2500-adc"; > + reg = <0x1e6e9000 0xb0>; Did you intend to change the size cell value here? It now matches the g4, but there was an explicit comment about the size for some reason in the -hunk below. It's probably worth an explicit call-out if we're going to change it. > + clocks = <&syscon ASPEED_CLK_APB>; See the clk comment on the g4 diff. Cheers, Andrew > + #io-channel-cells = <1>; > + status = "disabled"; > + }; > + > sram@1e720000 { > compatible = "mmio-sram"; > reg = <0x1e720000 0x9000>; // 36K > @@ -307,14 +315,6 @@ > no-loopback-test; > status = "disabled"; > }; > - > - adc: adc@1e6e9000 { > - compatible = "aspeed,ast2500-adc"; > - reg = <0x1e6e9000 0xb0>; > - clocks = <&clk_apb>; > - #io-channel-cells = <1>; > - status = "disabled"; > - }; > }; > }; > };
On Thu, 2017-09-28 at 17:21 +0930, Joel Stanley wrote: > Enable the buses that are in use and the devices that are attached. > Currently that includes the battery backed RTC, temperature > measurement > and EEPROM. > > Some of these buses are for hotplugged cards, such as PCIe cards. > Others do not yet have upstream drivers, so there are no devices > attached. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > --- > arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 48 > +++++++++++++++++++++++++++ > 1 file changed, 48 insertions(+) > > diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts > b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts > index 112551766275..e387c80b7f4f 100644 > --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts > +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts > @@ -61,3 +61,51 @@ > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_rmii1_default>; > }; > + > +&i2c0 { > + status = "okay"; > + > + eeprom@50 { > + compatible = "atmel,24c256"; > + reg = <0x50>; > + pagesize = <64>; > + }; > + > + rtc@68 { > + compatible = "dallas,ds3231"; > + reg = <0x68>; > + }; > +}; > + > +&i2c1 { > + status = "okay"; > +}; > + > +&i2c2 { > + status = "okay"; > + > + tmp423@4c { > + compatible = "ti,tmp423"; > + reg = <0x4c>; > + }; > +}; > + > +&i2c3 { > + status = "okay"; > +}; > + > +&i2c4 { > + status = "okay"; > +}; > + > +&i2c5 { > + status = "okay"; > +}; > + > +&i2c6 { > + status = "okay"; > +}; > + > +&i2c7 { > + status = "okay"; > +};
On Thu, 2017-09-28 at 17:21 +0930, Joel Stanley wrote: > Enable the buses that are in use and the devices that are attached. > Currently that includes temperature measurement and EEPROM. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > --- > arch/arm/boot/dts/aspeed-ast2500-evb.dts | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts > index 7c90dac99822..dc7d73b02b76 100644 > --- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts > +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts > @@ -59,3 +59,22 @@ > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>; > }; > + > +&i2c3 { > + status = "okay"; > + > + eeprom@50 { > + compatible = "atmel,24c08"; > + reg = <0x50>; > + pagesize = <16>; > + }; > +}; > + > +&i2c7 { > + status = "okay"; > + > + lm75@4d { > + compatible = "national,lm75"; > + reg = <0x4d>; > + }; > +};
On Thu, 2017-09-28 at 17:21 +0930, Joel Stanley wrote: > Existing userspace expects the console (UART5) to be at /dev/ttyS4. To > ensure the UARTs show up where users expect them, we give them fixed > aliases starting at 0. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> > --- > arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 4 ---- > arch/arm/boot/dts/aspeed-g4.dtsi | 5 +++++ > arch/arm/boot/dts/aspeed-g5.dtsi | 5 +++++ > 3 files changed, 10 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts > index e387c80b7f4f..be51be5a5f39 100644 > --- a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts > +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts > @@ -6,10 +6,6 @@ > model = "Palmetto BMC"; > compatible = "tyan,palmetto-bmc", "aspeed,ast2400"; > > - aliases { > - serial4 = &uart5; > - }; > - > chosen { > stdout-path = &uart5; > bootargs = "console=ttyS4,115200 earlyprintk"; > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi > index f8611d5a6465..191c33d18122 100644 > --- a/arch/arm/boot/dts/aspeed-g4.dtsi > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi > @@ -22,6 +22,11 @@ > i2c11 = &i2c11; > i2c12 = &i2c12; > i2c13 = &i2c13; > + serial0 = &uart1; > + serial1 = &uart2; > + serial2 = &uart3; > + serial3 = &uart4; > + serial4 = &uart5; > }; > > cpus { > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi > index de127370131d..251fc9f4637e 100644 > --- a/arch/arm/boot/dts/aspeed-g5.dtsi > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi > @@ -22,6 +22,11 @@ > i2c11 = &i2c11; > i2c12 = &i2c12; > i2c13 = &i2c13; > + serial0 = &uart1; > + serial1 = &uart2; > + serial2 = &uart3; > + serial3 = &uart4; > + serial4 = &uart5; > }; > > cpus {
On Wed, 2017-10-04 at 14:43 +0930, Joel Stanley wrote: > > > > > > + adc: adc@1e6e9000 { > > > + compatible = "aspeed,ast2500-adc"; > > > + reg = <0x1e6e9000 0xb0>; > > > > Did you intend to change the size cell value here? It now matches the g4, but > > there was an explicit comment about the size for some reason in the -hunk > > below. It's probably worth an explicit call-out if we're going to change it. > > Looks ok to me. Yeah, sorry, was looking in the wrong spot :/ Andrew
On Thu, 2017-09-28 at 17:21 +0930, Joel Stanley wrote: > - Shorten size of reg property so it covers only the implemented > registers > > - Add VUART compatible > > - Move stray uart1 in g5 definition > > - Remove outdated current-speed property. Different bootloaders use > different speeds, so this is no longer helpful > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > arch/arm/boot/dts/aspeed-g4.dtsi | 17 +++++++++-------- > arch/arm/boot/dts/aspeed-g5.dtsi | 36 ++++++++++++++++++------------------ > 2 files changed, 27 insertions(+), 26 deletions(-) > > diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi > index 191c33d18122..7a4a53666d70 100644 > --- a/arch/arm/boot/dts/aspeed-g4.dtsi > +++ b/arch/arm/boot/dts/aspeed-g4.dtsi > @@ -27,6 +27,7 @@ > serial2 = &uart3; > serial3 = &uart4; > serial4 = &uart5; > + serial5 = &vuart; > }; > > cpus { > @@ -199,7 +200,7 @@ > > uart1: serial@1e783000 { > compatible = "ns16550a"; > - reg = <0x1e783000 0x1000>; > + reg = <0x1e783000 0x20>; > reg-shift = <2>; > interrupts = <9>; > clocks = <&clk_uart>; > @@ -209,7 +210,7 @@ > > uart2: serial@1e78d000 { > compatible = "ns16550a"; > - reg = <0x1e78d000 0x1000>; > + reg = <0x1e78d000 0x20>; > reg-shift = <2>; > interrupts = <32>; > clocks = <&clk_uart>; > @@ -219,7 +220,7 @@ > > uart3: serial@1e78e000 { > compatible = "ns16550a"; > - reg = <0x1e78e000 0x1000>; > + reg = <0x1e78e000 0x20>; > reg-shift = <2>; > interrupts = <33>; > clocks = <&clk_uart>; > @@ -229,7 +230,7 @@ > > uart4: serial@1e78f000 { > compatible = "ns16550a"; > - reg = <0x1e78f000 0x1000>; > + reg = <0x1e78f000 0x20>; > reg-shift = <2>; > interrupts = <34>; > clocks = <&clk_uart>; > @@ -239,7 +240,7 @@ > > uart5: serial@1e784000 { > compatible = "ns16550a"; > - reg = <0x1e784000 0x1000>; > + reg = <0x1e784000 0x20>; > reg-shift = <2>; > interrupts = <10>; > clocks = <&clk_uart>; > @@ -248,9 +249,9 @@ > status = "disabled"; > }; > > - uart6: serial@1e787000 { > - compatible = "ns16550a"; > - reg = <0x1e787000 0x1000>; > + vuart: vuart@1e787000 { Bit of a nit, but arguably this should be `vuart: serial@...`? > + compatible = "aspeed,ast2400-vuart"; > + reg = <0x1e787000 0x40>; > reg-shift = <2>; > interrupts = <10>; > clocks = <&clk_uart>; > diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi > index 251fc9f4637e..0b793305120a 100644 > --- a/arch/arm/boot/dts/aspeed-g5.dtsi > +++ b/arch/arm/boot/dts/aspeed-g5.dtsi > @@ -27,6 +27,7 @@ > serial2 = &uart3; > serial3 = &uart4; > serial4 = &uart5; > + serial5 = &vuart; > }; > > cpus { > @@ -247,16 +248,6 @@ > status = "disabled"; > }; > > - uart1: serial@1e783000 { > - compatible = "ns16550a"; > - reg = <0x1e783000 0x1000>; > - reg-shift = <2>; > - interrupts = <9>; > - clocks = <&clk_uart>; > - no-loopback-test; > - status = "disabled"; > - }; > - > lpc: lpc@1e789000 { > compatible = "aspeed,ast2500-lpc", "simple-mfd"; > reg = <0x1e789000 0x1000>; > @@ -287,9 +278,19 @@ > }; > }; > > + uart1: serial@1e783000 { Earlier in the series you had a patch moving the ADC node to be in address-order with respect to the rest of the nodes but this change puts uart1 out of address-order. As it turns out the uarts blocks are sprayed around in the address-space: uart1 and uart5 are together, the vuart is elsewhere, then uarts 2-4 are lumped together in another spot. I think it makes sense to consolidate them, but it is inconsistent. Thoughts? > + compatible = "ns16550a"; > + reg = <0x1e783000 0x20>; > + reg-shift = <2>; > + interrupts = <9>; > + clocks = <&clk_uart>; > + no-loopback-test; > + status = "disabled"; > + }; > + > uart2: serial@1e78d000 { > compatible = "ns16550a"; > - reg = <0x1e78d000 0x1000>; > + reg = <0x1e78d000 0x20>; > reg-shift = <2>; > interrupts = <32>; > clocks = <&clk_uart>; > @@ -299,7 +300,7 @@ > > uart3: serial@1e78e000 { > compatible = "ns16550a"; > - reg = <0x1e78e000 0x1000>; > + reg = <0x1e78e000 0x20>; > reg-shift = <2>; > interrupts = <33>; > clocks = <&clk_uart>; > @@ -309,7 +310,7 @@ > > uart4: serial@1e78f000 { > compatible = "ns16550a"; > - reg = <0x1e78f000 0x1000>; > + reg = <0x1e78f000 0x20>; > reg-shift = <2>; > interrupts = <34>; > clocks = <&clk_uart>; > @@ -319,18 +320,17 @@ > > uart5: serial@1e784000 { > compatible = "ns16550a"; > - reg = <0x1e784000 0x1000>; > + reg = <0x1e784000 0x20>; > reg-shift = <2>; > interrupts = <10>; > clocks = <&clk_uart>; > - current-speed = <38400>; > no-loopback-test; > status = "disabled"; > }; > > - uart6: serial@1e787000 { > - compatible = "ns16550a"; > - reg = <0x1e787000 0x1000>; > + vuart: vuart@1e787000 { See serial@ comment above. Cheers, Andrew > + compatible = "aspeed,ast2500-vuart"; > + reg = <0x1e787000 0x40>; > reg-shift = <2>; > interrupts = <10>; > clocks = <&clk_uart>;
On Wed, Oct 4, 2017 at 2:58 PM, Andrew Jeffery <andrew@aj.id.au> wrote: > On Thu, 2017-09-28 at 17:21 +0930, Joel Stanley wrote: >> - uart6: serial@1e787000 { >> - compatible = "ns16550a"; >> - reg = <0x1e787000 0x1000>; >> + vuart: vuart@1e787000 { > > Bit of a nit, but arguably this should be `vuart: serial@...`? Yep, that makes sense. > >> + compatible = "aspeed,ast2400-vuart"; >> + reg = <0x1e787000 0x40>; >> reg-shift = <2>; >> interrupts = <10>; >> clocks = <&clk_uart>; >> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi >> index 251fc9f4637e..0b793305120a 100644 >> --- a/arch/arm/boot/dts/aspeed-g5.dtsi >> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi >> @@ -287,9 +278,19 @@ >> }; >> }; >> >> + uart1: serial@1e783000 { > > Earlier in the series you had a patch moving the ADC node to be in > address-order with respect to the rest of the nodes but this change puts uart1 > out of address-order. As it turns out the uarts blocks are sprayed around in > the address-space: uart1 and uart5 are together, the vuart is elsewhere, then > uarts 2-4 are lumped together in another spot. I think it makes sense to > consolidate them, but it is inconsistent. Thoughts? Yeah. I'll move them to where they should be. Cheers, Joel -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html