From patchwork Wed Sep 27 13:32:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shameerali Kolothum Thodi X-Patchwork-Id: 114368 Delivered-To: patch@linaro.org Received: by 10.140.106.117 with SMTP id d108csp5050287qgf; Wed, 27 Sep 2017 06:35:08 -0700 (PDT) X-Google-Smtp-Source: AOwi7QCVC0god2AOccPSAEkHdhNwfp80Ww5YhmiBDT3xwUaAd73eObGivL68dOHiHaqUdvsfEmLE X-Received: by 10.98.56.74 with SMTP id f71mr1397995pfa.44.1506519308733; Wed, 27 Sep 2017 06:35:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1506519308; cv=none; d=google.com; s=arc-20160816; b=JsOe1SM0A0nRNbWFwBQmnddeq8ejYxAcZrHIyUKia06yH1T88oRyeeTFwVEeixEBBM Gn3E7dId9X5wISykb0KOUhu7FSRz8prhZX0UDvOXOtO2/CYyVPkP9yScoW8ICHuoPtqF jdLpckdifMwQiiE5Vt4a8ABg7a3vfhfkJS5OIcrINJ9Xw1+W7Aah1pHz5494Rh+CEZzT GbrnxuhxxdHwWrxR7zRHk22o6lYwGLqVsJCKwl6jLcc3PsjDZ/n6lWcq1DPHW1nPPUyy BdugdoiZ7jnT0BuD7cq2wVHYzr3wEtDXPb1ADPHD9ZYU+4XHPykHKETzgYPiw5DitY/j lXSQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:message-id:date:subject:cc :to:from:arc-authentication-results; bh=uR5iT2FdLwYdVMA8hraqhjIKdWs/jIIuWt6YO+I3MO8=; b=JnEhYxGK/3k4RwRTp4LEGTxJBwAmeutTk7iuB4kYWtJ3sxbDqZYRyYwJL9uAruK8/Z pqrYoFx731iu7uN65HwB5Sa91zUepWjnHD4NrNqWaRh1yo8IYWk+zYbE9n0YcNRIXZwJ cn7zut017qZ+FrPhx0l8enBt3B6IzpydJeuiTzMV0tXFNxiWry7r3sXlzF9CCAf+iySW ZVLvdhExZbHV/vCR9oW55K34cVJP2yhZqaW7hEWRj0qrAruXUOXo9STdxPdWzWMsUPbv lB+UjG9BYOlqCM7+Jttu2dwOdwPqdmR//g0WMMv5Vk848ww01cS8zLwEyPqPnbpiiXcX vFVA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u9si7660961pge.139.2017.09.27.06.35.08; Wed, 27 Sep 2017 06:35:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752602AbdI0NfH (ORCPT + 6 others); Wed, 27 Sep 2017 09:35:07 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:7448 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751926AbdI0NfG (ORCPT ); Wed, 27 Sep 2017 09:35:06 -0400 Received: from 172.30.72.58 (EHLO DGGEMS401-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DIB16830; Wed, 27 Sep 2017 21:35:01 +0800 (CST) Received: from S00345302A-PC.china.huawei.com (10.203.177.212) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.301.0; Wed, 27 Sep 2017 21:34:53 +0800 From: Shameer Kolothum To: , , , , , , , CC: , , , , , , , , , , Shameer Kolothum Subject: [PATCH v8 0/5] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI) Date: Wed, 27 Sep 2017 14:32:36 +0100 Message-ID: <20170927133241.21036-1-shameerali.kolothum.thodi@huawei.com> X-Mailer: git-send-email 2.12.0.windows.1 MIME-Version: 1.0 X-Originating-IP: [10.203.177.212] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020205.59CBA905.01E5, ss=1, re=0.000, recu=0.000, reip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 30800b3d7090f53675d05f6e9940513b Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On certain HiSilicon platforms (hip06/hip07) the GIC ITS and PCIe RC deviates from the standard implementation and this breaks PCIe MSI functionality when SMMU is enabled. The HiSilicon erratum 161010801 describes this limitation of certain HiSilicon platforms to support the SMMU mappings for MSI transactions. On these platforms GICv3 ITS translator is presented with the deviceID by extending the MSI payload data to 64 bits to include the deviceID. Hence, the PCIe controller on this platforms has to differentiate the MSI payload against other DMA payload and has to modify the MSI payload. This basically makes it difficult for this platforms to have a SMMU translation for MSI. This patch implements an ACPI and DT based quirk to reserve the hw msi regions in the smmu-v3 driver which means these address regions will not be translated and will be excluded from iova allocations. To implement this quirk, the following changes are incorporated: 1. Added a generic helper function to IORT code to retrieve the associated ITS base address from a device IORT node. 2. Added a generic helper function to of iommu code to retrieve the associated msi controller base address from for a PCI RC msi-mapping and also platform device msi-parent. 3. Added quirk to SMMUv3 to retrieve the HW ITS address and replace the default SW MSI reserve address based on the IORT SMMU model or DT bindings. Changelog: v7 --> v8 Addressed comments from Rob and Lorenzo: -Modified to use DT compatible string for errata. -Changed logic to retrieve the msi-parent for DT case. v6 --> v7 Addressed request from Will to add DT support for the erratum: - added bt binding - add of_iommu_msi_get_resv_regions() New arm64 silicon errata entry Rename iort_iommu_{its->msi}_get_resv_regions v5 --> v6 Addressed comments from Robin and Lorenzo: -No change to patch#1 . -Reverted v5 patch#2 as this might break the platforms where this quirk is not applicable. Provided a generic function in iommu code and added back the quirk implementation in SMMU v3 driver(patch#3) v4 --> v5 Addressed comments from Robin and Lorenzo: -Added a comment to make it clear that, for now, only straightforward HW topologies are handled while reserving ITS regions(patch #1). v3 --> v4 Rebased on 4.13-rc1. Addressed comments from Robin, Will and Lorenzo: -As suggested by Robin, moved the ITS msi reservation into iommu_dma_get_resv_regions(). -Added its_count != resv region failure case(patch #1). v2 --> v3 Addressed comments from Lorenzo and Robin: -Removed dev_is_pci() check in smmuV3 driver. -Don't treat device not having an ITS mapping as an error in iort helper function. v1 --> v2 -patch 2/2: Invoke iort helper fn based on fwnode type(acpi). RFCv2 -->PATCH -Incorporated Lorenzo's review comments. RFC v1 --> RFC v2 Based on Robin's review comments, -Removed the generic erratum framework. -Using IORT/MADT tables to retrieve the ITS base addr instead of vendor specific CSRT table. John Garry (2): Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon erratum 161010801 iommu/of: Add msi address regions reservation helper Shameer Kolothum (3): ACPI/IORT: Add msi address regions reservation helper iommu/dma: Add a helper function to reserve HW MSI address regions for IOMMU drivers iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801 Documentation/arm64/silicon-errata.txt | 1 + .../devicetree/bindings/iommu/arm,smmu-v3.txt | 9 +- drivers/acpi/arm64/iort.c | 96 +++++++++++++++++++++- drivers/iommu/arm-smmu-v3.c | 41 +++++++-- drivers/iommu/dma-iommu.c | 19 +++++ drivers/iommu/of_iommu.c | 95 +++++++++++++++++++++ drivers/irqchip/irq-gic-v3-its.c | 3 +- include/linux/acpi_iort.h | 7 +- include/linux/dma-iommu.h | 7 ++ include/linux/of_iommu.h | 10 +++ 10 files changed, 276 insertions(+), 12 deletions(-) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Acked-by: Rob Herring