| Message ID | 1646644054-24421-1-git-send-email-hongxing.zhu@nxp.com |
|---|---|
| Headers | show |
| Series | Add the iMX8MP PCIe support | expand |
Hi Richard, Am Montag, dem 11.04.2022 um 03:32 +0000 schrieb Hongxing Zhu: > > -----Original Message----- > > From: Lucas Stach <l.stach@pengutronix.de> > > Sent: 2022年4月8日 16:13 > > To: Hongxing Zhu <hongxing.zhu@nxp.com>; tharvey@gateworks.com; > > Alexander Stein <alexander.stein@ew.tq-group.com> > > Cc: Philipp Zabel <p.zabel@pengutronix.de>; bhelgaas@google.com; > > Lorenzo > > Pieralisi <lorenzo.pieralisi@arm.com>; Rob Herring > > <robh@kernel.org>; Shawn > > Guo <shawnguo@kernel.org>; Vinod Koul <vkoul@kernel.org>; > > linux-phy@lists.infradead.org; Device Tree Mailing List > > <devicetree@vger.kernel.org>; linux-pci@vger.kernel.org; Linux ARM > > Mailing > > List <linux-arm-kernel@lists.infradead.org>; open list > > <linux-kernel@vger.kernel.org>; Sascha Hauer > > <kernel@pengutronix.de>; > > dl-linux-imx <linux-imx@nxp.com> > > Subject: Re: [PATCH v2 0/7] Add the iMX8MP PCIe support > > > > Am Freitag, dem 08.04.2022 um 03:14 +0000 schrieb Hongxing Zhu: > > > > > > [...] > > > > Richard, > > > > > > > > Thanks for working on this! > > > > > > > > Do you plan on submitting another version soon? I've tried to > > > > test > > > > this with an imx8mp board I'm bringing up and while the host > > > > controller enumerates I fail to get a link to a device. It's > > > > very > > > > likely I am missing something as this series depends on the > > > > IMX8MP blk-ctrl > > and gpc series which I also can't cleanly apply. > > > > Lucas just submitted a 'consolidated i.MX8MP HSIO/MEDIA/HDMI > > > > blk-ctrl series' [1] yet I can't find a repo/branch that > > > > applies to either. > > > > > > > > Perhaps you have a git repo somewhere I can look at while we > > > > wait > > > > for imx8mp blk-ctl/gpc to settle and you to submit a v3? > > > Hi Tim: > > > Thanks for your kindly help to do the tests. > > > I had listed the dependencies in the cover-letter log. > > > Alexander and I used to test this series commits based on the > > > V5.17 kernel. > > > > > > Lucas had provided some review comments and suggestions about the > > > PLL > > > bits > > > manipulations of HSIOMIX in i.MX8MP PCIe PHY driver #3 of this > > > series. > > > And he suggested to let the HSIOMIX blk-ctrl make this PLL as a > > > real > > > clock, > > > and used by i.MX8MP PCIe PHY driver later. > > > > > > Although I have some confusions, it's better let's wating for the > > > blk-ctrl settle down and get clear discussion with Lucas later. > > > How do you think about that? > > > > Just to let you know my plans: I was quite busy with getting the > > i.MX8MP > > HDMI part to work. Now that this is at least in a state where it > > can collect > > some feedback from upstream I have some time to circle back to this > > topic. I > > can't commit to do it immediately, but I'll get around to looking > > at the PCIe > > series a bit more in-depth and apply my HSIO PLL suggestion to the > > blk-ctrl > > driver during the next week. > > Hi Lucas: > Thanks for your helpful reply. > I know that you're busy with the blk-ctrl settle down now, and had > explained to > Tim. Yesterday I tried to get this series working on my 8MP-EVK board, but was unsuccessful for now. The PCIe link does not come up. PCIe REF_CLK is present and PERST de-asserted. I'm not sure if this is due to a faulty EP device (I don't have another M.2 KeyE device around to check) or if this may be due to the old revision of my 8MP-EVK, as I'm still working with a RevA board. The schematic revision log doesn't show anything that would obviously influence PCIe operation, but I have also not found any schematics for RevA. Do you know if there have been any PCIe related changes/fixes in the later EVK board revisions? For now I'll try to get this working on a custom i.MX8MP board, where I can use a different EP device. Maybe I'll have a bit more luck there. Regards, Lucas
> -----Original Message----- > From: Lucas Stach <l.stach@pengutronix.de> > Sent: 2022年4月13日 15:22 > To: Hongxing Zhu <hongxing.zhu@nxp.com>; tharvey@gateworks.com; > Alexander Stein <alexander.stein@ew.tq-group.com> > Cc: Philipp Zabel <p.zabel@pengutronix.de>; bhelgaas@google.com; Lorenzo > Pieralisi <lorenzo.pieralisi@arm.com>; Rob Herring <robh@kernel.org>; Shawn > Guo <shawnguo@kernel.org>; Vinod Koul <vkoul@kernel.org>; > linux-phy@lists.infradead.org; Device Tree Mailing List > <devicetree@vger.kernel.org>; linux-pci@vger.kernel.org; Linux ARM Mailing > List <linux-arm-kernel@lists.infradead.org>; open list > <linux-kernel@vger.kernel.org>; Sascha Hauer <kernel@pengutronix.de>; > dl-linux-imx <linux-imx@nxp.com> > Subject: Re: [PATCH v2 0/7] Add the iMX8MP PCIe support > > Hi Richard, > > Am Montag, dem 11.04.2022 um 03:32 +0000 schrieb Hongxing Zhu: > > > -----Original Message----- > > > From: Lucas Stach <l.stach@pengutronix.de> > > > Sent: 2022年4月8日 16:13 > > > To: Hongxing Zhu <hongxing.zhu@nxp.com>; tharvey@gateworks.com; > > > Alexander Stein <alexander.stein@ew.tq-group.com> > > > Cc: Philipp Zabel <p.zabel@pengutronix.de>; bhelgaas@google.com; > > > Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>; Rob Herring > > > <robh@kernel.org>; Shawn Guo <shawnguo@kernel.org>; Vinod Koul > > > <vkoul@kernel.org>; linux-phy@lists.infradead.org; Device Tree > > > Mailing List <devicetree@vger.kernel.org>; > > > linux-pci@vger.kernel.org; Linux ARM Mailing List > > > <linux-arm-kernel@lists.infradead.org>; open list > > > <linux-kernel@vger.kernel.org>; Sascha Hauer > > > <kernel@pengutronix.de>; dl-linux-imx <linux-imx@nxp.com> > > > Subject: Re: [PATCH v2 0/7] Add the iMX8MP PCIe support > > > > > > Am Freitag, dem 08.04.2022 um 03:14 +0000 schrieb Hongxing Zhu: > > > > > > > > [...] > > > > > Richard, > > > > > > > > > > Thanks for working on this! > > > > > > > > > > Do you plan on submitting another version soon? I've tried to > > > > > test this with an imx8mp board I'm bringing up and while the > > > > > host controller enumerates I fail to get a link to a device. > > > > > It's very likely I am missing something as this series depends > > > > > on the IMX8MP blk-ctrl > > > and gpc series which I also can't cleanly apply. > > > > > Lucas just submitted a 'consolidated i.MX8MP HSIO/MEDIA/HDMI > > > > > blk-ctrl series' [1] yet I can't find a repo/branch that applies > > > > > to either. > > > > > > > > > > Perhaps you have a git repo somewhere I can look at while we > > > > > wait for imx8mp blk-ctl/gpc to settle and you to submit a v3? > > > > Hi Tim: > > > > Thanks for your kindly help to do the tests. > > > > I had listed the dependencies in the cover-letter log. > > > > Alexander and I used to test this series commits based on the > > > > V5.17 kernel. > > > > > > > > Lucas had provided some review comments and suggestions about the > > > > PLL bits > > > > manipulations of HSIOMIX in i.MX8MP PCIe PHY driver #3 of this > > > > series. > > > > And he suggested to let the HSIOMIX blk-ctrl make this PLL as a > > > > real clock, > > > > and used by i.MX8MP PCIe PHY driver later. > > > > > > > > Although I have some confusions, it's better let's wating for the > > > > blk-ctrl settle down and get clear discussion with Lucas later. > > > > How do you think about that? > > > > > > Just to let you know my plans: I was quite busy with getting the > > > i.MX8MP HDMI part to work. Now that this is at least in a state > > > where it can collect some feedback from upstream I have some time to > > > circle back to this topic. I can't commit to do it immediately, but > > > I'll get around to looking at the PCIe series a bit more in-depth > > > and apply my HSIO PLL suggestion to the blk-ctrl driver during the > > > next week. > > > > Hi Lucas: > > Thanks for your helpful reply. > > I know that you're busy with the blk-ctrl settle down now, and had > > explained to Tim. > > Yesterday I tried to get this series working on my 8MP-EVK board, but was > unsuccessful for now. The PCIe link does not come up. PCIe REF_CLK is present > and PERST de-asserted. I'm not sure if this is due to a faulty EP device (I don't > have another M.2 KeyE device around to check) or if this may be due to the old > revision of my 8MP-EVK, as I'm still working with a RevA board. The schematic > revision log doesn't show anything that would obviously influence PCIe > operation, but I have also not found any schematics for RevA. > > Do you know if there have been any PCIe related changes/fixes in the later EVK > board revisions? > Hi Lucas: First of all, thanks a lot for your kindly help on this series. I remember that there is one PCIe related HW rework used to support the NVME device when Rev A board is used. Here is description of this rework and hope it's helpful. Support High power consumption NVMe SSD Current EVK has limitation to support high power consumption NVMe SSD, transient voltage drop is high, need to change R452 to 0ohm to solve this issue. Rework Steps: Change R452 to 470-75394 0ohm, 0402 BTW, R452 is placed just at the right side of the M.2 slot. Best Regards Richard Zhu > For now I'll try to get this working on a custom i.MX8MP board, where I can > use a different EP device. Maybe I'll have a bit more luck there. > > Regards, > Lucas
> -----Original Message----- > From: Lucas Stach <l.stach@pengutronix.de> > Sent: 2022年4月15日 4:45 > To: Hongxing Zhu <hongxing.zhu@nxp.com>; p.zabel@pengutronix.de; > bhelgaas@google.com; lorenzo.pieralisi@arm.com; robh@kernel.org; > shawnguo@kernel.org; vkoul@kernel.org; alexander.stein@ew.tq-group.com > Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org; > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx > <linux-imx@nxp.com> > Subject: Re: [PATCH v2 0/7] Add the iMX8MP PCIe support > > Hi Richard, > > I didn't get around to see what's wrong with the PCIe on my EVK, so I wasn't > able to do any reworks to the series. As I will be on vacation from tomorrow > until Apr. 25th, I'll just leave some more comments on this series for your > consideration. Hi Lucas: Got that, thanks. Have a good holiday. Best Regards Richard Zhu > > Regards, > Lucas > > Am Montag, dem 07.03.2022 um 17:07 +0800 schrieb Richard Zhu: > > Based on the i.MX8MP GPC and blk-ctrl patch-set[1] issued by Lucas and > > the following commits. > > - one codes refine patch-set[5]. > > - two Fixes[2],[3]. > > - one binding commit[4]. > > - some dts changes in Shawn's git if you want to test PCIe on i.MX8MM > EVK. > > b4d36c10bf17 arm64: dts: imx8mm-evk: Add the pcie support on > imx8mm evk board > > aaeba6a8e226 arm64: dts: imx8mm: Add the pcie support > > cfc5078432ca arm64: dts: imx8mm: Add the pcie phy support > > > > Sorry about that there may be some conflictions when do the codes merge. > > I'm waiting for the ack now, and will re-base them in a proper sequence later. > > > > This series patches add the i.MX8MP PCIe support and tested on i.MX8MM > > EVK and i.MX8MP EVk boards. The PCIe NVME works fine on both boards. > > > > - i.MX8MP PCIe PHY has two resets refer to the i.MX8MM PCIe PHY. > > Add one more PHY reset for i.MX8MP PCIe PHY accordingly. > > - Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver. > > And share as much as possible codes with i.MX8MM PCIe PHY. > > - Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe > > driver. > > > > Main changes v1-->v2: > > - It's my fault forget including Vinod, re-send v2 after include Vinod > > and linux-phy@lists.infradead.org. > > - List the basements of this patch-set. The branch, codes changes and so on. > > - Clean up some useless register and bit definitions in #3 patch. > > > > [1]https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fp > > > atchwork.kernel.org%2Fproject%2Flinux-arm-kernel%2Fcover%2F2022022820 > 1 > > > 731.3330192-1-l.stach%40pengutronix.de%2F&data=04%7C01%7Chongx > ing. > > > zhu%40nxp.com%7C3e8710b45fcd4516145908da1e57ad9b%7C686ea1d3bc2 > b4c6fa92 > > > cd99c5c301635%7C0%7C1%7C637855659162145906%7CUnknown%7CTWF > pbGZsb3d8eyJ > > > WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7 > C3000 > > > &sdata=p758ZvzD9wSh23Bcz29e%2BbvVi6BfmvDqIgh4yzR3ACs%3D&am > p;reserv > > ed=0 > > [2]https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fp > > > atchwork.ozlabs.org%2Fproject%2Flinux-pci%2Fpatch%2F1646289275-17813- > 1 > > > -git-send-email-hongxing.zhu%40nxp.com%2F&data=04%7C01%7Chongxi > ng. > > > zhu%40nxp.com%7C3e8710b45fcd4516145908da1e57ad9b%7C686ea1d3bc2 > b4c6fa92 > > > cd99c5c301635%7C0%7C1%7C637855659162145906%7CUnknown%7CTWF > pbGZsb3d8eyJ > > > WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7 > C3000 > > > &sdata=PKa0bhjfgg%2B74KtKYEtMLtar%2BMkw6od3IZkkjd5U6fM%3D&a > mp;rese > > rved=0 > > [3]https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fp > > > atchwork.ozlabs.org%2Fproject%2Flinux-pci%2Fpatch%2F1645672013-8949-1 > - > > > git-send-email-hongxing.zhu%40nxp.com%2F&data=04%7C01%7Chongxi > ng.z > > > hu%40nxp.com%7C3e8710b45fcd4516145908da1e57ad9b%7C686ea1d3bc2 > b4c6fa92c > > > d99c5c301635%7C0%7C1%7C637855659162145906%7CUnknown%7CTWFp > bGZsb3d8eyJW > > > IjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3 > 000& > > > amp;sdata=wCnAZqH22CWRBc%2BNJOTdfFUEcGcb9JtziIVJsUMSXVc%3D& > ;reserve > > d=0 > > [4]https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fp > > > atchwork.ozlabs.org%2Fproject%2Flinux-pci%2Fpatch%2F1646293805-18248- > 1 > > > -git-send-email-hongxing.zhu%40nxp.com%2F&data=04%7C01%7Chongxi > ng. > > > zhu%40nxp.com%7C3e8710b45fcd4516145908da1e57ad9b%7C686ea1d3bc2 > b4c6fa92 > > > cd99c5c301635%7C0%7C1%7C637855659162145906%7CUnknown%7CTWF > pbGZsb3d8eyJ > > > WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7 > C3000 > > > &sdata=U221NuIhee%2FF9Yf%2B28pFwVlg8fi3m694qbdfPZs%2BHEw%3 > D&re > > served=0 > > [5]https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fp > > > atchwork.ozlabs.org%2Fproject%2Flinux-pci%2Fcover%2F1645760667-10510- > 1 > > > -git-send-email-hongxing.zhu%40nxp.com%2F&data=04%7C01%7Chongxi > ng. > > > zhu%40nxp.com%7C3e8710b45fcd4516145908da1e57ad9b%7C686ea1d3bc2 > b4c6fa92 > > > cd99c5c301635%7C0%7C1%7C637855659162145906%7CUnknown%7CTWF > pbGZsb3d8eyJ > > > WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7 > C3000 > > > &sdata=9KHzoq6kMFAL%2FVnG6GMvY%2FdbfzaOlZf9y4Y%2FuVrEKV4%3 > D&re > > served=0 > > > > NOTE: > > Based git > > <git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git> > > Based branch <pci/imx6> > > > > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 1 + > > Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 4 +- > > arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 55 > ++++++++++++++++++++++ > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46 > ++++++++++++++++++- > > drivers/pci/controller/dwc/pci-imx6.c | 19 > +++++++- > > drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 205 > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++----------------- > > drivers/reset/reset-imx7.c | 1 + > > 7 files changed, 286 insertions(+), 45 deletions(-) > > > > [PATCH v2 1/7] reset: imx7: Add the iMX8MP PCIe PHY PERST support > > [PATCH v2 2/7] dt-binding: phy: Add iMX8MP PCIe PHY binding [PATCH v2 > > 3/7] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY [PATCH v2 4/7] > > dt-bindings: imx6q-pcie: Add iMX8MP PCIe compatible [PATCH v2 5/7] > > arm64: dts: imx8mp: add the iMX8MP PCIe support [PATCH v2 6/7] arm64: > > dts: imx8mp-evk: Add PCIe support [PATCH v2 7/7] PCI: imx6: Add the > > iMX8MP PCIe support >
On Sun, Apr 17, 2022 at 10:00 PM Hongxing Zhu <hongxing.zhu@nxp.com> wrote: > > > -----Original Message----- > > From: Lucas Stach <l.stach@pengutronix.de> > > Sent: 2022年4月15日 5:03 > > To: Hongxing Zhu <hongxing.zhu@nxp.com>; p.zabel@pengutronix.de; > > bhelgaas@google.com; lorenzo.pieralisi@arm.com; robh@kernel.org; > > shawnguo@kernel.org; vkoul@kernel.org; alexander.stein@ew.tq-group.com > > Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org; > > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx > > <linux-imx@nxp.com> > > Subject: Re: [PATCH v2 5/7] arm64: dts: imx8mp: add the iMX8MP PCIe > > support > > > > Am Montag, dem 07.03.2022 um 17:07 +0800 schrieb Richard Zhu: > > > Add the i.MX8MP PCIe support. > > > > > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > > > --- > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46 > > > ++++++++++++++++++++++- > > > 1 file changed, 45 insertions(+), 1 deletion(-) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > index b40a5646f205..e7b3d8029e34 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi > > > @@ -5,6 +5,7 @@ > > > > > > #include <dt-bindings/clock/imx8mp-clock.h> > > > #include <dt-bindings/power/imx8mp-power.h> > > > +#include <dt-bindings/reset/imx8mp-reset.h> > > > #include <dt-bindings/gpio/gpio.h> > > > #include <dt-bindings/input/input.h> > > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > > @@ -375,7 +376,8 @@ iomuxc: pinctrl@30330000 { > > > }; > > > > > > gpr: iomuxc-gpr@30340000 { > > > - compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; > > > + compatible = "fsl,imx8mp-iomuxc-gpr", > > > + "fsl,imx6q-iomuxc-gpr", "syscon"; > > > reg = <0x30340000 0x10000>; > > > }; > > > > > > @@ -965,6 +967,17 @@ aips4: bus@32c00000 { > > > #size-cells = <1>; > > > ranges; > > > > > > + pcie_phy: pcie-phy@32f00000 { > > > + compatible = "fsl,imx8mp-pcie-phy"; > > > + reg = <0x32f00000 0x10000>; > > > + resets = <&src IMX8MP_RESET_PCIEPHY>, > > > + <&src IMX8MP_RESET_PCIEPHY_PERST>; > > > + reset-names = "pciephy", "perst"; > > > + power-domains = <&hsio_blk_ctrl > > IMX8MP_HSIOBLK_PD_PCIE_PHY>; > > > + #phy-cells = <0>; > > > + status = "disabled"; > > > + }; > > > + > > > hsio_blk_ctrl: blk-ctrl@32f10000 { > > > compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; > > > reg = <0x32f10000 0x24>; > > > @@ -980,6 +993,37 @@ hsio_blk_ctrl: blk-ctrl@32f10000 { > > > }; > > > }; > > > > > > + pcie: pcie@33800000 { > > > + compatible = "fsl,imx8mp-pcie"; > > > + reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; > > > + reg-names = "dbi", "config"; > > > + #address-cells = <3>; > > > + #size-cells = <2>; > > > + device_type = "pci"; > > > + bus-range = <0x00 0xff>; > > > + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 > > 0x00010000 /* downstream I/O 64KB */ > > > + 0x82000000 0 0x18000000 0x18000000 0 > > 0x07f00000>; /* non-prefetchable memory */ > > > + num-lanes = <1>; > > > + num-viewport = <4>; > > > + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; > > > + interrupt-names = "msi"; > > > + #interrupt-cells = <1>; > > > + interrupt-map-mask = <0 0 0 0x7>; > > > + interrupt-map = <0 0 0 1 &gic GIC_SPI 126 > > IRQ_TYPE_LEVEL_HIGH>, > > > + <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > > > + <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, > > > + <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; > > > + fsl,max-link-speed = <3>; > > > > I believe that imx6_pcie_start_link does not properly handle Gen3 speeds. > Good caught. > The according link_gen condition should be changed in driver too. > Would be changed in next version. > Thanks. > > Best Regards > Richard Zhu > > > > Regards, > > Lucas > > > > > + linux,pci-domain = <0>; > > > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; > > > + resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, > > > + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; > > > + reset-names = "apps", "turnoff"; > > > + phys = <&pcie_phy>; > > > + phy-names = "pcie-phy"; > > > + status = "disabled"; > > > + }; > > > + > > > gpu3d: gpu@38000000 { > > > compatible = "vivante,gc"; > > > reg = <0x38000000 0x8000>; > > > Richard, Do you have an updated series for IMX8MP PCIe yet? I believe everything you were waiting on is now merged (blk-ctrl and power-domain). Best Regards, Tim
Based on the i.MX8MP GPC and blk-ctrl patch-set[1] issued by Lucas and the following commits. - one codes refine patch-set[5]. - two Fixes[2],[3]. - one binding commit[4]. - some dts changes in Shawn's git if you want to test PCIe on i.MX8MM EVK. b4d36c10bf17 arm64: dts: imx8mm-evk: Add the pcie support on imx8mm evk board aaeba6a8e226 arm64: dts: imx8mm: Add the pcie support cfc5078432ca arm64: dts: imx8mm: Add the pcie phy support Sorry about that there may be some conflictions when do the codes merge. I'm waiting for the ack now, and will re-base them in a proper sequence later. This series patches add the i.MX8MP PCIe support and tested on i.MX8MM EVK and i.MX8MP EVk boards. The PCIe NVME works fine on both boards. - i.MX8MP PCIe PHY has two resets refer to the i.MX8MM PCIe PHY. Add one more PHY reset for i.MX8MP PCIe PHY accordingly. - Add the i.MX8MP PCIe PHY support in the i.MX8M PCIe PHY driver. And share as much as possible codes with i.MX8MM PCIe PHY. - Add the i.MX8MP PCIe support in binding document, DTS files, and PCIe driver. Main changes v1-->v2: - It's my fault forget including Vinod, re-send v2 after include Vinod and linux-phy@lists.infradead.org. - List the basements of this patch-set. The branch, codes changes and so on. - Clean up some useless register and bit definitions in #3 patch. [1]https://patchwork.kernel.org/project/linux-arm-kernel/cover/20220228201731.3330192-1-l.stach@pengutronix.de/ [2]https://patchwork.ozlabs.org/project/linux-pci/patch/1646289275-17813-1-git-send-email-hongxing.zhu@nxp.com/ [3]https://patchwork.ozlabs.org/project/linux-pci/patch/1645672013-8949-1-git-send-email-hongxing.zhu@nxp.com/ [4]https://patchwork.ozlabs.org/project/linux-pci/patch/1646293805-18248-1-git-send-email-hongxing.zhu@nxp.com/ [5]https://patchwork.ozlabs.org/project/linux-pci/cover/1645760667-10510-1-git-send-email-hongxing.zhu@nxp.com/ NOTE: Based git <git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git> Based branch <pci/imx6> Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 1 + Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml | 4 +- arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 55 ++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 46 ++++++++++++++++++- drivers/pci/controller/dwc/pci-imx6.c | 19 +++++++- drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 205 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------- drivers/reset/reset-imx7.c | 1 + 7 files changed, 286 insertions(+), 45 deletions(-) [PATCH v2 1/7] reset: imx7: Add the iMX8MP PCIe PHY PERST support [PATCH v2 2/7] dt-binding: phy: Add iMX8MP PCIe PHY binding [PATCH v2 3/7] phy: freescale: imx8m-pcie: Add iMX8MP PCIe PHY [PATCH v2 4/7] dt-bindings: imx6q-pcie: Add iMX8MP PCIe compatible [PATCH v2 5/7] arm64: dts: imx8mp: add the iMX8MP PCIe support [PATCH v2 6/7] arm64: dts: imx8mp-evk: Add PCIe support [PATCH v2 7/7] PCI: imx6: Add the iMX8MP PCIe support