| Message ID | 1614773878-8058-1-git-send-email-rnayak@codeaurora.org |
|---|---|
| Headers | show |
| Series | Add binding updates and DT files for SC7280 SoC | expand |
Quoting Rajendra Nayak (2021-03-03 04:17:47) > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > new file mode 100644 > index 0000000..4a56d9c > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -0,0 +1,299 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * sc7280 SoC device tree source > + * > + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. > + */ > + > +#include <dt-bindings/clock/qcom,gcc-sc7280.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + chosen { }; > + > + clocks { > + xo_board: xo-board { > + compatible = "fixed-clock"; > + clock-frequency = <76800000>; If this is the correct frequency I think we need to update the rpmh clk driver to use the correct divider? Right now I think it is a 2 when it should be 4? > + #clock-cells = <0>; > + }; > + > + sleep_clk: sleep-clk { > + compatible = "fixed-clock"; > + clock-frequency = <32000>; > + #clock-cells = <0>; > + }; > + };
Quoting Rajendra Nayak (2021-03-03 04:17:56) > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index fe4fdb9..aa6f847 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -239,6 +239,25 @@ > interrupt-controller; > }; > > + spmi_bus: spmi@c440000 { > + compatible = "qcom,spmi-pmic-arb"; > + reg = <0 0x0c440000 0 0x1100>, > + <0 0x0c600000 0 0x2000000>, > + <0 0x0e600000 0 0x100000>, > + <0 0x0e700000 0 0xa0000>, > + <0 0x0c40a000 0 0x26000>; > + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; > + interrupt-names = "periph_irq"; > + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; > + qcom,ee = <0>; > + qcom,channel = <0>; > + #address-cells = <1>; > + #size-cells = <1>; I see the binding says these should be 2 instead of 1 but I suspect that is incorrect. > + interrupt-controller; > + #interrupt-cells = <4>; > + cell-index = <0>; Is cell-index used? Please remove as I don't see it used anywhere and not in the binding. > + }; > + > tlmm: pinctrl@f100000 { > compatible = "qcom,sc7280-pinctrl"; > reg = <0 0x0f100000 0 0x1000000>;
On 3/4/2021 5:42 AM, Stephen Boyd wrote: > Quoting Rajendra Nayak (2021-03-03 04:17:56) >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index fe4fdb9..aa6f847 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -239,6 +239,25 @@ >> interrupt-controller; >> }; >> >> + spmi_bus: spmi@c440000 { >> + compatible = "qcom,spmi-pmic-arb"; >> + reg = <0 0x0c440000 0 0x1100>, >> + <0 0x0c600000 0 0x2000000>, >> + <0 0x0e600000 0 0x100000>, >> + <0 0x0e700000 0 0xa0000>, >> + <0 0x0c40a000 0 0x26000>; >> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; >> + interrupt-names = "periph_irq"; >> + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; >> + qcom,ee = <0>; >> + qcom,channel = <0>; >> + #address-cells = <1>; >> + #size-cells = <1>; > > I see the binding says these should be 2 instead of 1 but I suspect that > is incorrect. yeah looks like the bindings need to be fixed > >> + interrupt-controller; >> + #interrupt-cells = <4>; >> + cell-index = <0>; > > Is cell-index used? Please remove as I don't see it used anywhere and > not in the binding. I'll drop it. thanks > >> + }; >> + >> tlmm: pinctrl@f100000 { >> compatible = "qcom,sc7280-pinctrl"; >> reg = <0 0x0f100000 0 0x1000000>;
On Wed, 03 Mar 2021 17:47:48 +0530, Rajendra Nayak wrote: > Add the compatible string for sc7180 SoC from Qualcomm > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > --- > Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org>
On Wed, 03 Mar 2021 17:47:51 +0530, Rajendra Nayak wrote: > From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > > Add the SoC specific compatible for SC7280 implementing > arm,mmu-500. > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > --- > Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org>
On Wed, 03 Mar 2021 17:47:54 +0530, Rajendra Nayak wrote: > From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > > Add compatible for watchdog timer on SC7280 SoC. > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > --- > Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org>
On 3/4/2021 5:37 AM, Stephen Boyd wrote: > Quoting Rajendra Nayak (2021-03-03 04:17:47) >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> new file mode 100644 >> index 0000000..4a56d9c >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -0,0 +1,299 @@ >> +// SPDX-License-Identifier: BSD-3-Clause >> +/* >> + * sc7280 SoC device tree source >> + * >> + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. >> + */ >> + >> +#include <dt-bindings/clock/qcom,gcc-sc7280.h> >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> +/ { >> + interrupt-parent = <&intc>; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + chosen { }; >> + >> + clocks { >> + xo_board: xo-board { >> + compatible = "fixed-clock"; >> + clock-frequency = <76800000>; > > If this is the correct frequency I think we need to update the rpmh clk > driver to use the correct divider? Right now I think it is a 2 when it > should be 4? Looks like this is fixed now [1] [1] https://lore.kernel.org/patchwork/patch/1393159/ > >> + #clock-cells = <0>; >> + }; >> + >> + sleep_clk: sleep-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <32000>; >> + #clock-cells = <0>; >> + }; >> + }; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation