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Fri, 11 Dec 2020 01:54:41 +0000 From: Liu Ying To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Cc: kishon@ti.com, vkoul@kernel.org, robh+dt@kernel.org, a.hajda@samsung.com, narmstrong@baylibre.com, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@siol.net, airlied@linux.ie, daniel@ffwll.ch, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, agx@sigxcpu.org, robert.chiras@nxp.com, martin.kepplinger@puri.sm Subject: [PATCH v3 0/5] phy: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support Date: Fri, 11 Dec 2020 09:46:17 +0800 Message-Id: <1607651182-12307-1-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2P153CA0042.APCP153.PROD.OUTLOOK.COM (2603:1096:4:c6::11) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by SG2P153CA0042.APCP153.PROD.OUTLOOK.COM (2603:1096:4:c6::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3676.5 via Frontend Transport; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: J3mGief3m79kPwuuMy4NNmWnA/Ow6z0vaHLn9fwPbZ9POOi+VyZo0CufyNOCvec/E8kn4QThVBAw1cvgXPwfrRhlYd/ctjaXpCYtAFmf55rdYR6NN/U6qXV0acdiwpIIt9RzdCQvJz1/JHx6UNSaOqgf/uX0Wx2ExuPC6VEK2scycYAvLbO3rNhgbgfsXCL7j6pRsD4HYSISxm8vlLsYlNyaTcTCVHosiKc8dS3AmJxFMLkTsAdSuZikqrrfnkHHbCAUYAVxALZB6Ys7ELu+45ftaI7XZ1glFw3kt8oVNSebeZ0XQ3iolwO3PYr9DF5Y6NnZfU3j2xP8t7HKXa+Ab+TrV2zKs+8c62BnYQNftPOEDunvvLDil9XDY5fWuTb4Nm7zR+hXK7CawRRPKl+K30qdmp3yDgCdWoryRCs2vq4FmS0j1DUYlZeCHgeD8+Jv54Dbwsr5nxsN+sPEgLxmr5LZqQnEhZXKqk41KeYqyJsNxqglM6Hf8zF8415RbHMNUMLQ00fXKz8FbIaEyHSrUph00pnzPaanrwQgJ34MJgvbJBZvqKKhZaOmJHrwZ1tItEeyv5BPzB9y5rMLv4f+Qcov/6T0njSUqbmR5yNxCFZAueLoa+fmVg4cml4NQ5tuUWh3eM2M4VqEXrHJDKJ6jStFPnpxCJ0a2IFHn+eq6qGcNvL/SvX0s89NyxTZ2efJObY4TJUyjqsd95g7rZzxLNUZcMDC+PgLVuX45X6MxTAsoHRS4myM5t9qhgytaDkbc+DGbkd0JQXxLUyhoznuoir00in3oOeMin1TQfdx6SIKzc6y3sJaYtoGplTLquop8/t3cCJ5TNHUvpwQE4KfWKtrU5fq2Q9SR7buI0MAPz94ag/wJLJklNmpVbDlYmSNhfMe+PAub9O3NigTDMjlCc/6Qr8VdeAej+F8iN3XrfQx2ISRAhqsG+lqrqhZFBUtp0fWcOoeGoziJ5UqZNEQoJwYIAvytN2ve4sIe2vLn6zTBXvsyenVd4DomXYP67w/ X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB3983.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2020 01:54:41.5653 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-Network-Message-Id: 9190fcdc-9e45-487b-ac04-08d89d77b9d5 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: eFbjMN4vuar18vQ1xwpfOsShUvd2FiG8Igo8VmdiRB9hcDcyriu4S6+BfAsYxzxaqmCxNkOsj5zHF950e00ThQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0402MB3952 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi, This series adds i.MX8qxp LVDS PHY mode support for the Mixel PHY in the Freescale i.MX8qxp SoC. The Mixel PHY is MIPI DPHY + LVDS PHY combo, which can works in either MIPI DPHY mode or LVDS PHY mode. The PHY mode is controlled by i.MX8qxp SCU firmware. The PHY driver would call a SCU function to configure the mode. The PHY driver is already supporting the Mixel MIPI DPHY in i.MX8mq SoC, where it appears to be a single MIPI DPHY. Patch 1/5 sets PHY mode in the Northwest Logic MIPI DSI host controller bridge driver, since i.MX8qxp SoC embeds this controller IP to support MIPI DSI displays together with the Mixel PHY. Patch 2/5 allows LVDS PHYs to be configured through the generic PHY functions and through a custom structure added to the generic PHY configuration union. Patch 3/5 converts mixel,mipi-dsi-phy plain text dt binding to json-schema. Patch 4/5 adds dt binding support for the Mixel combo PHY in i.MX8qxp SoC. Patch 5/5 adds the i.MX8qxp LVDS PHY mode support in the Mixel PHY driver. Welcome comments, thanks. v2->v3: * Improve readability of mixel_dphy_set_mode() in the Mixel PHY driver. (Guido) * Improve the 'clock-names' property in the PHY dt binding. v1->v2: * Convert mixel,mipi-dsi-phy plain text dt binding to json-schema. (Guido) * Print invalid PHY mode in dmesg from the Mixel PHY driver. (Guido) * Add Guido's R-b tag on the patch for the nwl-dsi drm bridge driver. Liu Ying (5): drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_enable() phy: Add LVDS configuration options dt-bindings: phy: Convert mixel,mipi-dsi-phy to json-schema dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for i.MX8qxp phy: freescale: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support .../devicetree/bindings/phy/mixel,mipi-dsi-phy.txt | 29 --- .../bindings/phy/mixel,mipi-dsi-phy.yaml | 107 ++++++++ drivers/gpu/drm/bridge/nwl-dsi.c | 6 + drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c | 269 ++++++++++++++++++++- include/linux/phy/phy-lvds.h | 48 ++++ include/linux/phy/phy.h | 4 + 6 files changed, 423 insertions(+), 40 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml create mode 100644 include/linux/phy/phy-lvds.h Reviewed-by: Robert Foss