| Message ID | 1607651182-12307-1-git-send-email-victor.liu@nxp.com |
|---|---|
| Headers | show |
| Series | phy: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support | expand |
Hey Liu, This patch seems to be included in both this series and the "Add some DRM bridge drivers support for i.MX8qm/qxp SoCs" series. Instead of having the two series have a conflict I would suggest either merging them (if that makes sense) or removing this patch from one of them and explicitly stating that there is a dependency on the other series. (the patch itself still looks good though :) ) On Fri, 11 Dec 2020 at 02:56, Liu Ying <victor.liu@nxp.com> wrote: > > This patch allows LVDS PHYs to be configured through > the generic functions and through a custom structure > added to the generic union. > > The parameters added here are based on common LVDS PHY > implementation practices. The set of parameters > should cover all potential users. > > Cc: Kishon Vijay Abraham I <kishon@ti.com> > Cc: Vinod Koul <vkoul@kernel.org> > Cc: NXP Linux Team <linux-imx@nxp.com> > Signed-off-by: Liu Ying <victor.liu@nxp.com> > --- > v2->v3: > * No change. > > v1->v2: > * No change. > > include/linux/phy/phy-lvds.h | 48 ++++++++++++++++++++++++++++++++++++++++++++ > include/linux/phy/phy.h | 4 ++++ > 2 files changed, 52 insertions(+) > create mode 100644 include/linux/phy/phy-lvds.h > > diff --git a/include/linux/phy/phy-lvds.h b/include/linux/phy/phy-lvds.h > new file mode 100644 > index 00000000..1b5b9d6 > --- /dev/null > +++ b/include/linux/phy/phy-lvds.h > @@ -0,0 +1,48 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright 2020 NXP > + */ > + > +#ifndef __PHY_LVDS_H_ > +#define __PHY_LVDS_H_ > + > +/** > + * struct phy_configure_opts_lvds - LVDS configuration set > + * > + * This structure is used to represent the configuration state of a > + * LVDS phy. > + */ > +struct phy_configure_opts_lvds { > + /** > + * @bits_per_lane_and_dclk_cycle: > + * > + * Number of bits per data lane and differential clock cycle. > + */ > + unsigned int bits_per_lane_and_dclk_cycle; > + > + /** > + * @differential_clk_rate: > + * > + * Clock rate, in Hertz, of the LVDS differential clock. > + */ > + unsigned long differential_clk_rate; > + > + /** > + * @lanes: > + * > + * Number of active, consecutive, data lanes, starting from > + * lane 0, used for the transmissions. > + */ > + unsigned int lanes; > + > + /** > + * @is_slave: > + * > + * Boolean, true if the phy is a slave which works together > + * with a master phy to support dual link transmission, > + * otherwise a regular phy or a master phy. > + */ > + bool is_slave; > +}; > + > +#endif /* __PHY_LVDS_H_ */ > diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h > index e435bdb..d450b44 100644 > --- a/include/linux/phy/phy.h > +++ b/include/linux/phy/phy.h > @@ -17,6 +17,7 @@ > #include <linux/regulator/consumer.h> > > #include <linux/phy/phy-dp.h> > +#include <linux/phy/phy-lvds.h> > #include <linux/phy/phy-mipi-dphy.h> > > struct phy; > @@ -51,10 +52,13 @@ enum phy_mode { > * the MIPI_DPHY phy mode. > * @dp: Configuration set applicable for phys supporting > * the DisplayPort protocol. > + * @lvds: Configuration set applicable for phys supporting > + * the LVDS phy mode. > */ > union phy_configure_opts { > struct phy_configure_opts_mipi_dphy mipi_dphy; > struct phy_configure_opts_dp dp; > + struct phy_configure_opts_lvds lvds; > }; > > /** > -- > 2.7.4 >
Hey Liu, Looking at this series[1], all but patch#2 has been reviewed, and #2 looks good to me. So I think this series is ready to have v4 re-spun and and all of the r-bs from v3 added to the relevant patches. [1] https://patchwork.kernel.org/project/dri-devel/cover/1607651182-12307-1-git-send-email-victor.liu@nxp.com/ On Fri, 19 Feb 2021 at 10:22, Liu Ying <victor.liu@nxp.com> wrote: > > A gentle ping. > > Vinod, Kishon, it would be nice if you may help review this. > > Thanks, > Liu Ying > > On Fri, 2020-12-11 at 09:46 +0800, Liu Ying wrote: > > Hi, > > > > This series adds i.MX8qxp LVDS PHY mode support for the Mixel PHY in the > > Freescale i.MX8qxp SoC. > > > > The Mixel PHY is MIPI DPHY + LVDS PHY combo, which can works in either > > MIPI DPHY mode or LVDS PHY mode. The PHY mode is controlled by i.MX8qxp > > SCU firmware. The PHY driver would call a SCU function to configure the > > mode. > > > > The PHY driver is already supporting the Mixel MIPI DPHY in i.MX8mq SoC, > > where it appears to be a single MIPI DPHY. > > > > > > Patch 1/5 sets PHY mode in the Northwest Logic MIPI DSI host controller > > bridge driver, since i.MX8qxp SoC embeds this controller IP to support > > MIPI DSI displays together with the Mixel PHY. > > > > Patch 2/5 allows LVDS PHYs to be configured through the generic PHY functions > > and through a custom structure added to the generic PHY configuration union. > > > > Patch 3/5 converts mixel,mipi-dsi-phy plain text dt binding to json-schema. > > > > Patch 4/5 adds dt binding support for the Mixel combo PHY in i.MX8qxp SoC. > > > > Patch 5/5 adds the i.MX8qxp LVDS PHY mode support in the Mixel PHY driver. > > > > > > Welcome comments, thanks. > > > > v2->v3: > > * Improve readability of mixel_dphy_set_mode() in the Mixel PHY driver. (Guido) > > * Improve the 'clock-names' property in the PHY dt binding. > > > > v1->v2: > > * Convert mixel,mipi-dsi-phy plain text dt binding to json-schema. (Guido) > > * Print invalid PHY mode in dmesg from the Mixel PHY driver. (Guido) > > * Add Guido's R-b tag on the patch for the nwl-dsi drm bridge driver. > > > > Liu Ying (5): > > drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_enable() > > phy: Add LVDS configuration options > > dt-bindings: phy: Convert mixel,mipi-dsi-phy to json-schema > > dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for > > i.MX8qxp > > phy: freescale: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode > > support > > > > .../devicetree/bindings/phy/mixel,mipi-dsi-phy.txt | 29 --- > > .../bindings/phy/mixel,mipi-dsi-phy.yaml | 107 ++++++++ > > drivers/gpu/drm/bridge/nwl-dsi.c | 6 + > > drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c | 269 ++++++++++++++++++++- > > include/linux/phy/phy-lvds.h | 48 ++++ > > include/linux/phy/phy.h | 4 + > > 6 files changed, 423 insertions(+), 40 deletions(-) > > delete mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt > > create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml > > create mode 100644 include/linux/phy/phy-lvds.h > > >
On Fri, 5 Mar 2021 at 16:03, Robert Foss <robert.foss@linaro.org> wrote: > > Hey Liu, > > This patch seems to be included in both this series and the "Add some > DRM bridge drivers support for i.MX8qm/qxp SoCs" series. Instead of > having the two series have a conflict I would suggest either merging > them (if that makes sense) or removing this patch from one of them and > explicitly stating that there is a dependency on the other series. > > (the patch itself still looks good though :) ) After having looked through the rest of the series, and seeing it is pretty much ready to be merged. Feel free to add my r-b to this patch. Reviewed-by: Robert Foss <robert.foss@linaro.org> > > On Fri, 11 Dec 2020 at 02:56, Liu Ying <victor.liu@nxp.com> wrote: > > > > This patch allows LVDS PHYs to be configured through > > the generic functions and through a custom structure > > added to the generic union. > > > > The parameters added here are based on common LVDS PHY > > implementation practices. The set of parameters > > should cover all potential users. > > > > Cc: Kishon Vijay Abraham I <kishon@ti.com> > > Cc: Vinod Koul <vkoul@kernel.org> > > Cc: NXP Linux Team <linux-imx@nxp.com> > > Signed-off-by: Liu Ying <victor.liu@nxp.com> > > --- > > v2->v3: > > * No change. > > > > v1->v2: > > * No change. > > > > include/linux/phy/phy-lvds.h | 48 ++++++++++++++++++++++++++++++++++++++++++++ > > include/linux/phy/phy.h | 4 ++++ > > 2 files changed, 52 insertions(+) > > create mode 100644 include/linux/phy/phy-lvds.h > > > > diff --git a/include/linux/phy/phy-lvds.h b/include/linux/phy/phy-lvds.h > > new file mode 100644 > > index 00000000..1b5b9d6 > > --- /dev/null > > +++ b/include/linux/phy/phy-lvds.h > > @@ -0,0 +1,48 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright 2020 NXP > > + */ > > + > > +#ifndef __PHY_LVDS_H_ > > +#define __PHY_LVDS_H_ > > + > > +/** > > + * struct phy_configure_opts_lvds - LVDS configuration set > > + * > > + * This structure is used to represent the configuration state of a > > + * LVDS phy. > > + */ > > +struct phy_configure_opts_lvds { > > + /** > > + * @bits_per_lane_and_dclk_cycle: > > + * > > + * Number of bits per data lane and differential clock cycle. > > + */ > > + unsigned int bits_per_lane_and_dclk_cycle; > > + > > + /** > > + * @differential_clk_rate: > > + * > > + * Clock rate, in Hertz, of the LVDS differential clock. > > + */ > > + unsigned long differential_clk_rate; > > + > > + /** > > + * @lanes: > > + * > > + * Number of active, consecutive, data lanes, starting from > > + * lane 0, used for the transmissions. > > + */ > > + unsigned int lanes; > > + > > + /** > > + * @is_slave: > > + * > > + * Boolean, true if the phy is a slave which works together > > + * with a master phy to support dual link transmission, > > + * otherwise a regular phy or a master phy. > > + */ > > + bool is_slave; > > +}; > > + > > +#endif /* __PHY_LVDS_H_ */ > > diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h > > index e435bdb..d450b44 100644 > > --- a/include/linux/phy/phy.h > > +++ b/include/linux/phy/phy.h > > @@ -17,6 +17,7 @@ > > #include <linux/regulator/consumer.h> > > > > #include <linux/phy/phy-dp.h> > > +#include <linux/phy/phy-lvds.h> > > #include <linux/phy/phy-mipi-dphy.h> > > > > struct phy; > > @@ -51,10 +52,13 @@ enum phy_mode { > > * the MIPI_DPHY phy mode. > > * @dp: Configuration set applicable for phys supporting > > * the DisplayPort protocol. > > + * @lvds: Configuration set applicable for phys supporting > > + * the LVDS phy mode. > > */ > > union phy_configure_opts { > > struct phy_configure_opts_mipi_dphy mipi_dphy; > > struct phy_configure_opts_dp dp; > > + struct phy_configure_opts_lvds lvds; > > }; > > > > /** > > -- > > 2.7.4 > >
On Fri, 2021-03-05 at 16:03 +0100, Robert Foss wrote: > Hey Liu, > > This patch seems to be included in both this series and the "Add some > DRM bridge drivers support for i.MX8qm/qxp SoCs" series. Instead of > having the two series have a conflict I would suggest either merging > them (if that makes sense) or removing this patch from one of them and > explicitly stating that there is a dependency on the other series. I choose not to merge them, because they are self-contained respectively and splitting them makes the patch number(14) of the "Add some DRM bridge drivers support for i.MX8qm/qxp SoCs" series look better. I guess this series will land prior to the other one, so I would drop this patch from that series and state the dependency there(actually, I mentioned I also sent this patch via this series there). > > (the patch itself still looks good though :) ) Thanks for your review :) Liu Ying > > On Fri, 11 Dec 2020 at 02:56, Liu Ying <victor.liu@nxp.com> wrote: > > This patch allows LVDS PHYs to be configured through > > the generic functions and through a custom structure > > added to the generic union. > > > > The parameters added here are based on common LVDS PHY > > implementation practices. The set of parameters > > should cover all potential users. > > > > Cc: Kishon Vijay Abraham I <kishon@ti.com> > > Cc: Vinod Koul <vkoul@kernel.org> > > Cc: NXP Linux Team <linux-imx@nxp.com> > > Signed-off-by: Liu Ying <victor.liu@nxp.com> > > --- > > v2->v3: > > * No change. > > > > v1->v2: > > * No change. > > > > include/linux/phy/phy-lvds.h | 48 ++++++++++++++++++++++++++++++++++++++++++++ > > include/linux/phy/phy.h | 4 ++++ > > 2 files changed, 52 insertions(+) > > create mode 100644 include/linux/phy/phy-lvds.h > > > > diff --git a/include/linux/phy/phy-lvds.h b/include/linux/phy/phy-lvds.h > > new file mode 100644 > > index 00000000..1b5b9d6 > > --- /dev/null > > +++ b/include/linux/phy/phy-lvds.h > > @@ -0,0 +1,48 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +/* > > + * Copyright 2020 NXP > > + */ > > + > > +#ifndef __PHY_LVDS_H_ > > +#define __PHY_LVDS_H_ > > + > > +/** > > + * struct phy_configure_opts_lvds - LVDS configuration set > > + * > > + * This structure is used to represent the configuration state of a > > + * LVDS phy. > > + */ > > +struct phy_configure_opts_lvds { > > + /** > > + * @bits_per_lane_and_dclk_cycle: > > + * > > + * Number of bits per data lane and differential clock cycle. > > + */ > > + unsigned int bits_per_lane_and_dclk_cycle; > > + > > + /** > > + * @differential_clk_rate: > > + * > > + * Clock rate, in Hertz, of the LVDS differential clock. > > + */ > > + unsigned long differential_clk_rate; > > + > > + /** > > + * @lanes: > > + * > > + * Number of active, consecutive, data lanes, starting from > > + * lane 0, used for the transmissions. > > + */ > > + unsigned int lanes; > > + > > + /** > > + * @is_slave: > > + * > > + * Boolean, true if the phy is a slave which works together > > + * with a master phy to support dual link transmission, > > + * otherwise a regular phy or a master phy. > > + */ > > + bool is_slave; > > +}; > > + > > +#endif /* __PHY_LVDS_H_ */ > > diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h > > index e435bdb..d450b44 100644 > > --- a/include/linux/phy/phy.h > > +++ b/include/linux/phy/phy.h > > @@ -17,6 +17,7 @@ > > #include <linux/regulator/consumer.h> > > > > #include <linux/phy/phy-dp.h> > > +#include <linux/phy/phy-lvds.h> > > #include <linux/phy/phy-mipi-dphy.h> > > > > struct phy; > > @@ -51,10 +52,13 @@ enum phy_mode { > > * the MIPI_DPHY phy mode. > > * @dp: Configuration set applicable for phys supporting > > * the DisplayPort protocol. > > + * @lvds: Configuration set applicable for phys supporting > > + * the LVDS phy mode. > > */ > > union phy_configure_opts { > > struct phy_configure_opts_mipi_dphy mipi_dphy; > > struct phy_configure_opts_dp dp; > > + struct phy_configure_opts_lvds lvds; > > }; > > > > /** > > -- > > 2.7.4 > >
Hi, This series adds i.MX8qxp LVDS PHY mode support for the Mixel PHY in the Freescale i.MX8qxp SoC. The Mixel PHY is MIPI DPHY + LVDS PHY combo, which can works in either MIPI DPHY mode or LVDS PHY mode. The PHY mode is controlled by i.MX8qxp SCU firmware. The PHY driver would call a SCU function to configure the mode. The PHY driver is already supporting the Mixel MIPI DPHY in i.MX8mq SoC, where it appears to be a single MIPI DPHY. Patch 1/5 sets PHY mode in the Northwest Logic MIPI DSI host controller bridge driver, since i.MX8qxp SoC embeds this controller IP to support MIPI DSI displays together with the Mixel PHY. Patch 2/5 allows LVDS PHYs to be configured through the generic PHY functions and through a custom structure added to the generic PHY configuration union. Patch 3/5 converts mixel,mipi-dsi-phy plain text dt binding to json-schema. Patch 4/5 adds dt binding support for the Mixel combo PHY in i.MX8qxp SoC. Patch 5/5 adds the i.MX8qxp LVDS PHY mode support in the Mixel PHY driver. Welcome comments, thanks. v2->v3: * Improve readability of mixel_dphy_set_mode() in the Mixel PHY driver. (Guido) * Improve the 'clock-names' property in the PHY dt binding. v1->v2: * Convert mixel,mipi-dsi-phy plain text dt binding to json-schema. (Guido) * Print invalid PHY mode in dmesg from the Mixel PHY driver. (Guido) * Add Guido's R-b tag on the patch for the nwl-dsi drm bridge driver. Liu Ying (5): drm/bridge: nwl-dsi: Set PHY mode in nwl_dsi_enable() phy: Add LVDS configuration options dt-bindings: phy: Convert mixel,mipi-dsi-phy to json-schema dt-bindings: phy: mixel: mipi-dsi-phy: Add Mixel combo PHY support for i.MX8qxp phy: freescale: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support .../devicetree/bindings/phy/mixel,mipi-dsi-phy.txt | 29 --- .../bindings/phy/mixel,mipi-dsi-phy.yaml | 107 ++++++++ drivers/gpu/drm/bridge/nwl-dsi.c | 6 + drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c | 269 ++++++++++++++++++++- include/linux/phy/phy-lvds.h | 48 ++++ include/linux/phy/phy.h | 4 + 6 files changed, 423 insertions(+), 40 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.yaml create mode 100644 include/linux/phy/phy-lvds.h