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[23.128.96.18]) by mx.google.com with ESMTP id m23si5058939edq.564.2020.08.07.03.25.30; Fri, 07 Aug 2020 03:25:30 -0700 (PDT) Received-SPF: pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of devicetree-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727081AbgHGKZ3 (ORCPT + 6 others); Fri, 7 Aug 2020 06:25:29 -0400 Received: from mx.socionext.com ([202.248.49.38]:31561 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726619AbgHGKZ3 (ORCPT ); Fri, 7 Aug 2020 06:25:29 -0400 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 07 Aug 2020 19:25:27 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id E8E1560060; Fri, 7 Aug 2020 19:25:27 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Fri, 7 Aug 2020 19:25:27 +0900 Received: from plum.e01.socionext.com (unknown [10.213.132.32]) by kinkan.css.socionext.com (Postfix) with ESMTP id 749781A0507; Fri, 7 Aug 2020 19:25:27 +0900 (JST) From: Kunihiko Hayashi To: Lorenzo Pieralisi , Bjorn Helgaas , Jingoo Han , Gustavo Pimentel , Rob Herring , Masahiro Yamada , Marc Zyngier Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Masami Hiramatsu , Jassi Brar , Kunihiko Hayashi Subject: [PATCH v6 0/6] PCI: uniphier: Add features for UniPhier PCIe host controller Date: Fri, 7 Aug 2020 19:25:16 +0900 Message-Id: <1596795922-705-1-git-send-email-hayashi.kunihiko@socionext.com> X-Mailer: git-send-email 2.7.4 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This series adds some features for UniPhier PCIe host controller. - Add support for PME and AER invoked by MSI interrupt - Add iATU register view support for PCIe version >= 4.80 - Add an error message when failing to get phy driver This adds a new function called by MSI handler in DesignWare PCIe framework, that invokes PME and AER funcions to detect the factor from SoC-dependent registers. Changes since v5: - Add pcie_port_service_get_irq() function to pcie/portdrv - Call pcie_port_service_get_irq() to get vIRQ interrupt number for PME/AER - Rebase to the latest linux-next branch, and remove devm_platform_ioremap_resource_byname() replacement patch Changes since v4: - Add Acked-by: line to dwc patch Changes since v3: - Move msi_host_isr() call into dw_handle_msi_irq() - Move uniphier_pcie_misc_isr() call into the guard of chained_irq - Use a bool argument is_msi instead of pci_msi_enabled() - Consolidate handler calls for the same interrupt - Fix typos in commit messages Changes since v2: - Avoid printing phy error message in case of EPROBE_DEFER - Fix iATU register mapping method - dt-bindings: Add Acked-by: line - Fix typos in commit messages - Use devm_platform_ioremap_resource_byname() Changes since v1: - Add check if struct resource is NULL - Fix warning in the type of dev_err() argument Kunihiko Hayashi (6): PCI: portdrv: Add pcie_port_service_get_irq() function PCI: dwc: Add msi_host_isr() callback PCI: uniphier: Add misc interrupt handler to invoke PME and AER dt-bindings: PCI: uniphier: Add iATU register description PCI: uniphier: Add iATU register support PCI: uniphier: Add error message when failed to get phy .../devicetree/bindings/pci/uniphier-pcie.txt | 1 + drivers/pci/controller/dwc/pcie-designware-host.c | 3 + drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/controller/dwc/pcie-uniphier.c | 90 ++++++++++++++++++---- drivers/pci/pcie/portdrv.h | 1 + drivers/pci/pcie/portdrv_core.c | 16 ++++ 6 files changed, 99 insertions(+), 13 deletions(-) -- 2.7.4