From patchwork Fri Feb 7 09:20:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Macpaul Lin X-Patchwork-Id: 205061 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92723C3F68F for ; Fri, 7 Feb 2020 09:23:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6A34E20838 for ; Fri, 7 Feb 2020 09:23:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="NppQX57f" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726573AbgBGJXi (ORCPT ); Fri, 7 Feb 2020 04:23:38 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:39177 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726417AbgBGJXh (ORCPT ); Fri, 7 Feb 2020 04:23:37 -0500 X-UUID: 48944d527b0e4c689738fe6c9b65d3ad-20200207 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=U8FRwP71b/QLr9XY8BWqKkhHb2z9q2xa/koQUBK/dBI=; b=NppQX57femOoZqrCThFU6mK3Iez7kVuIQh+bFga/JdK7FMGBlnK3f7iA0EB8C4EDy7mmeZrhzKI4f7oUvhJ1B73RCRyk/1x5chgiM0XZVO7GK3bj3ZtgMjooHqbl0CENrhtRWC1Uwfp1TFflZ3TwmJuYYvH08aGIqK+tHmEaP74=; X-UUID: 48944d527b0e4c689738fe6c9b65d3ad-20200207 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 2137306294; Fri, 07 Feb 2020 17:23:32 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 7 Feb 2020 17:24:18 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 7 Feb 2020 17:22:49 +0800 From: Macpaul Lin To: Rob Herring , Mark Rutland , Matthias Brugger , Catalin Marinas , Will Deacon , Michael Turquette , Stephen Boyd , mtk01761 , Fabien Parent , Weiyi Lu , Mars Cheng , Sean Wang , Macpaul Lin , Owen Chen , Chunfeng Yun , "Evan Green" , Yong Wu , Joerg Roedel , Shawn Guo , Marc Zyngier , Ryder Lee , , , , , CC: Mediatek WSD Upstream , CC Hwang , Loda Chou Subject: [PATCH v7 0/7] Add basic SoC support for mt6765 Date: Fri, 7 Feb 2020 17:20:43 +0800 Message-ID: <1581067250-12744-1-git-send-email-macpaul.lin@mediatek.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch adds basic SoC support for Mediatek's new 8-core SoC, MT6765, which is mainly for smartphone application. Changes in V7: 1. Adapt V6's patchset to latest kernel tree 5.5-rc1. Origin V6 patchset: https://patchwork.kernel.org/cover/11041963/ 2. Correct 2 clock-controller type in documentation: mipi0 and venc_gcon. [v7 1/7] dt-bindings: clock: mediatek: document clk bindings 3. Remove V6's patch 03 because it has been taken into 5.5-next-soc [v6, 03/08] dt-bindings: mediatek: add MT6765 power dt-bindings 3. Update Reviewed-by: Rob Herring for [v6, 04/08] clk: mediatek: add mt6765 clock IDs --> [v7, 03/07] clk: mediatek: add mt6765 clock IDs 4. Update SPDX tag for [v6, 05/08] clk: mediatek: Add MT6765 clock support --> [v7, 04/07] clk: mediatek: Add MT6765 clock support Changes in V6: 1. Adapt V5's patchset to latest kernel tree. Origin V5 patchset. https://lore.kernel.org/patchwork/cover/963612/ 2. Due to clk's common code has been submit by other platform, this patch set will have dependencies with the following patchsets as the following orders. 2.a. [v8,00/21] MT8183 IOMMU SUPPORT https://patchwork.kernel.org/cover/11023585/ 2.b. [v11,0/6] Add basic node support for Mediatek MT8183 SoC https://patchwork.kernel.org/cover/10962385/ 2.c. [v6,00/14] Mediatek MT8183 scpsys support https://patchwork.kernel.org/cover/11005751/ 3. Correct power related patches into dt-binding patches. 4. Re-order V5's 4/11, 6/11, and 7/11 due clk common code change and make dependencies in order. 5. Update some commit message in clk related patches. Changes in V5: 1. add clk support Changes in V4: 1. add gic's settings in reg properties 2. remove some patches about dt-bindings since GKH already took them Changes in V3: 1. split dt-binding document patchs 2. fix mt6765.dtsi warnings with W=12 3. remove uncessary PPI affinity for timer 4. add gicc base for gic dt node Changes in V2: 1. fix clk properties in uart dts node 2. fix typo in submit title 3. add simple-bus in mt6765.dtsi 4. use correct SPDX license format Mars Cheng (5): dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC dt-bindings: mediatek: Add smi dts binding for Mediatek MT6765 SoC clk: mediatek: add mt6765 clock IDs soc: mediatek: add MT6765 scpsys and subdomain support arm64: dts: mediatek: add mt6765 support Owen Chen (2): clk: mediatek: Add MT6765 clock support arm64: defconfig: add CONFIG_COMMON_CLK_MT6765_XXX clocks .../arm/mediatek/mediatek,apmixedsys.txt | 1 + .../bindings/arm/mediatek/mediatek,audsys.txt | 1 + .../bindings/arm/mediatek/mediatek,camsys.txt | 1 + .../bindings/arm/mediatek/mediatek,imgsys.txt | 1 + .../arm/mediatek/mediatek,infracfg.txt | 1 + .../bindings/arm/mediatek/mediatek,mipi0a.txt | 28 + .../bindings/arm/mediatek/mediatek,mmsys.txt | 1 + .../arm/mediatek/mediatek,pericfg.txt | 1 + .../arm/mediatek/mediatek,topckgen.txt | 1 + .../arm/mediatek/mediatek,vcodecsys.txt | 27 + .../mediatek,smi-common.txt | 1 + arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt6765-evb.dts | 33 + arch/arm64/boot/dts/mediatek/mt6765.dtsi | 253 +++++ arch/arm64/configs/defconfig | 6 + drivers/clk/mediatek/Kconfig | 86 ++ drivers/clk/mediatek/Makefile | 7 + drivers/clk/mediatek/clk-mt6765-audio.c | 100 ++ drivers/clk/mediatek/clk-mt6765-cam.c | 74 ++ drivers/clk/mediatek/clk-mt6765-img.c | 70 ++ drivers/clk/mediatek/clk-mt6765-mipi0a.c | 68 ++ drivers/clk/mediatek/clk-mt6765-mm.c | 96 ++ drivers/clk/mediatek/clk-mt6765-vcodec.c | 70 ++ drivers/clk/mediatek/clk-mt6765.c | 952 ++++++++++++++++++ drivers/soc/mediatek/mtk-scpsys.c | 130 +++ include/dt-bindings/clock/mt6765-clk.h | 313 ++++++ 26 files changed, 2323 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mipi0a.txt create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt create mode 100644 arch/arm64/boot/dts/mediatek/mt6765-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt6765.dtsi create mode 100644 drivers/clk/mediatek/clk-mt6765-audio.c create mode 100644 drivers/clk/mediatek/clk-mt6765-cam.c create mode 100644 drivers/clk/mediatek/clk-mt6765-img.c create mode 100644 drivers/clk/mediatek/clk-mt6765-mipi0a.c create mode 100644 drivers/clk/mediatek/clk-mt6765-mm.c create mode 100644 drivers/clk/mediatek/clk-mt6765-vcodec.c create mode 100644 drivers/clk/mediatek/clk-mt6765.c create mode 100644 include/dt-bindings/clock/mt6765-clk.h -- 2.18.0