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Mon, 9 Sep 2024 09:27:50 GMT Received: from hu-mdalam-blr.qualcomm.com (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 9 Sep 2024 02:27:46 -0700 From: Md Sadre Alam To: , , , , , , , , , , , , , , CC: Subject: [PATCH v4 08/11] crypto: qce - Add LOCK and UNLOCK flag support Date: Mon, 9 Sep 2024 14:56:29 +0530 Message-ID: <20240909092632.2776160-9-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240909092632.2776160-1-quic_mdalam@quicinc.com> References: <20240909092632.2776160-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: VNKSFYDRR6fTRj0FBHHfTMZtm-oZeOrc X-Proofpoint-GUID: VNKSFYDRR6fTRj0FBHHfTMZtm-oZeOrc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 malwarescore=0 adultscore=0 mlxlogscore=999 suspectscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2408220000 definitions=main-2409090075 Add LOCK and UNLOCK flag support while preapring command descriptor for writing crypto register. added qce_bam_acquire_lock() and qce_bam_release_lock() which will do dummy write to a crypto register for acquiring lock and releaseing lock. Signed-off-by: Md Sadre Alam --- Change in [v4] * Added qce_bam_acquire_lock() and qce_bam_release_lock() api Change in [v3] * No change Change in [v2] * Added initial support for LOCK/UNLOCK flag on command descriptor Change in [v1] * This patch was not included in [v1] drivers/crypto/qce/common.c | 35 +++++++++++++++++++++++++++++++++++ drivers/crypto/qce/core.h | 2 ++ drivers/crypto/qce/dma.c | 7 ++++++- drivers/crypto/qce/dma.h | 2 ++ 4 files changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index ff96f6ba1fc5..dad12e15905f 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -588,6 +588,41 @@ int qce_start(struct crypto_async_request *async_req, u32 type) #define STATUS_ERRORS \ (BIT(SW_ERR_SHIFT) | BIT(AXI_ERR_SHIFT) | BIT(HSD_ERR_SHIFT)) +int qce_bam_acquire_lock(struct qce_device *qce) +{ + int ret; + + qce_clear_bam_transaction(qce); + + /* This is just a dummy write to acquire lock on bam pipe */ + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, 0, 1); + ret = qce_submit_cmd_desc(qce, QCE_DMA_DESC_FLAG_LOCK); + if (ret) { + dev_err(qce->dev, "Error in Locking cmd descriptor\n"); + return ret; + } + + return 0; +} + +int qce_bam_release_lock(struct qce_device *qce) +{ + int ret; + + qce_clear_bam_transaction(qce); + + /* This just dummy write to release lock on bam pipe*/ + qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, 0, 1); + + ret = qce_submit_cmd_desc(qce, QCE_DMA_DESC_FLAG_UNLOCK); + if (ret) { + dev_err(qce->dev, "Error in Un-Locking cmd descriptor\n"); + return ret; + } + + return 0; +} + int qce_check_status(struct qce_device *qce, u32 *status) { int ret = 0; diff --git a/drivers/crypto/qce/core.h b/drivers/crypto/qce/core.h index bf28dedd1509..d01d810b60ad 100644 --- a/drivers/crypto/qce/core.h +++ b/drivers/crypto/qce/core.h @@ -68,4 +68,6 @@ int qce_read_reg_dma(struct qce_device *qce, unsigned int offset, void *buff, void qce_clear_bam_transaction(struct qce_device *qce); int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags); struct qce_bam_transaction *qce_alloc_bam_txn(struct qce_dma_data *dma); +int qce_bam_acquire_lock(struct qce_device *qce); +int qce_bam_release_lock(struct qce_device *qce); #endif /* _CORE_H_ */ diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index e4e672d65302..93d455d1d5b4 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -72,7 +72,12 @@ int qce_submit_cmd_desc(struct qce_device *qce, unsigned long flags) unsigned long desc_flags; int ret = 0; - desc_flags = DMA_PREP_CMD; + if (flags & QCE_DMA_DESC_FLAG_LOCK) + desc_flags = DMA_PREP_CMD | DMA_PREP_LOCK; + else if (flags & QCE_DMA_DESC_FLAG_UNLOCK) + desc_flags = DMA_PREP_CMD | DMA_PREP_UNLOCK; + else + desc_flags = DMA_PREP_CMD; /* For command descriptor always use consumer pipe * it recomended as per HPG diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index f10991590b3f..ad8a18a720b1 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -19,6 +19,8 @@ #define QCE_BAM_CMD_ELEMENT_SIZE 64 #define QCE_DMA_DESC_FLAG_BAM_NWD (0x0004) #define QCE_MAX_REG_READ 8 +#define QCE_DMA_DESC_FLAG_LOCK (0x0002) +#define QCE_DMA_DESC_FLAG_UNLOCK (0x0001) struct qce_result_dump { u32 auth_iv[QCE_AUTHIV_REGS_CNT];