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Thu, 15 Aug 2024 08:57:29 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 40xkmhenmk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:29 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 47F8vSWL029645; Thu, 15 Aug 2024 08:57:28 GMT Received: from hu-devc-blr-u22-a.qualcomm.com (hu-mdalam-blr.qualcomm.com [10.131.36.157]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 47F8vSOU029643 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 15 Aug 2024 08:57:28 +0000 Received: by hu-devc-blr-u22-a.qualcomm.com (Postfix, from userid 466583) id 96F6041254; Thu, 15 Aug 2024 14:27:27 +0530 (+0530) From: Md Sadre Alam To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, thara.gopinath@gmail.com, herbert@gondor.apana.org.au, davem@davemloft.net, gustavoars@kernel.org, u.kleine-koenig@pengutronix.de, kees@kernel.org, agross@kernel.org, linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com, quic_mdalam@quicinc.com, quic_utiwari@quicinc.com Subject: [PATCH v2 03/16] dmaengine: qcom: bam_dma: add LOCK & UNLOCK flag support Date: Thu, 15 Aug 2024 14:27:12 +0530 Message-Id: <20240815085725.2740390-4-quic_mdalam@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240815085725.2740390-1-quic_mdalam@quicinc.com> References: <20240815085725.2740390-1-quic_mdalam@quicinc.com> Precedence: bulk X-Mailing-List: linux-crypto@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: BCo9da2oaL2nPsP4y9QAtOnGpzMarqE- X-Proofpoint-ORIG-GUID: BCo9da2oaL2nPsP4y9QAtOnGpzMarqE- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-15_01,2024-08-13_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 mlxscore=0 suspectscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 impostorscore=0 mlxlogscore=916 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408150064 Add lock and unlock flag support on command descriptor. Once lock set in requester pipe, then the bam controller will lock all others pipe and process the request only from requester pipe. Unlocking only can be performed from the same pipe. If DMA_PREP_LOCK flag passed in command descriptor then requester of this transaction wanted to lock the BAM controller for this transaction so BAM driver should set LOCK bit for the HW descriptor. If DMA_PREP_UNLOCK flag passed in command descriptor then requester of this transaction wanted to unlock the BAM controller.so BAM driver should set UNLOCK bit for the HW descriptor. Signed-off-by: Md Sadre Alam --- Change in [v2] * Added LOCK and UNLOCK flag in bam driver Change in [v1] * This patch was not included in [v1] drivers/dma/qcom/bam_dma.c | 10 +++++++++- include/linux/dmaengine.h | 6 ++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index 1ac7e250bdaa..ab3b5319aa68 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -58,6 +58,8 @@ struct bam_desc_hw { #define DESC_FLAG_EOB BIT(13) #define DESC_FLAG_NWD BIT(12) #define DESC_FLAG_CMD BIT(11) +#define DESC_FLAG_LOCK BIT(10) +#define DESC_FLAG_UNLOCK BIT(9) struct bam_async_desc { struct virt_dma_desc vd; @@ -692,9 +694,15 @@ static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan, unsigned int curr_offset = 0; do { - if (flags & DMA_PREP_CMD) + if (flags & DMA_PREP_CMD) { desc->flags |= cpu_to_le16(DESC_FLAG_CMD); + if (bdev->bam_pipe_lock && flags & DMA_PREP_LOCK) + desc->flags |= cpu_to_le16(DESC_FLAG_LOCK); + else if (bdev->bam_pipe_lock && flags & DMA_PREP_UNLOCK) + desc->flags |= cpu_to_le16(DESC_FLAG_UNLOCK); + } + desc->addr = cpu_to_le32(sg_dma_address(sg) + curr_offset); diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index b137fdb56093..70f23068bfdc 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -200,6 +200,10 @@ struct dma_vec { * transaction is marked with DMA_PREP_REPEAT will cause the new transaction * to never be processed and stay in the issued queue forever. The flag is * ignored if the previous transaction is not a repeated transaction. + * @DMA_PREP_LOCK: tell the driver that there is a lock bit set on command + * descriptor. + * @DMA_PREP_UNLOCK: tell the driver that there is a un-lock bit set on command + * descriptor. */ enum dma_ctrl_flags { DMA_PREP_INTERRUPT = (1 << 0), @@ -212,6 +216,8 @@ enum dma_ctrl_flags { DMA_PREP_CMD = (1 << 7), DMA_PREP_REPEAT = (1 << 8), DMA_PREP_LOAD_EOT = (1 << 9), + DMA_PREP_LOCK = (1 << 10), + DMA_PREP_UNLOCK = (1 << 11), }; /**