From patchwork Tue Oct 10 12:57:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 731508 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C6C7CD80D1 for ; Tue, 10 Oct 2023 13:02:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232505AbjJJNCu (ORCPT ); Tue, 10 Oct 2023 09:02:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47688 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232266AbjJJNCU (ORCPT ); Tue, 10 Oct 2023 09:02:20 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FBE3FC; Tue, 10 Oct 2023 06:02:11 -0700 (PDT) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 39A88gwi001194; Tue, 10 Oct 2023 15:01:18 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=UsshDYP9Oqyxk+2EV7ru90DdWl28I8GlDHnWNqkU7MY=; b=TE edYziWEWSj3lCxmnFBsto/43XWyTMpKaBArYHTLdbdfGTcR9ry2D/vBqGxnrTxY5 VUo8A2agpqhWuy21Ql2U168a4DfOOtX+QyD27gfHLxZt17yzcDPSrL0rJLmNbcKB K1KjMcRtDYXv1ZLrgX6weidGafFp+OPoNnK4DCnPoWdt6LaG2U9KBoFrY4VQSXEv xyDeXkXGRud+vu930gEYWmxLb+NmKYz+cp5UR5Jh64zJzM4udaEtZlGAoSDKgQAt gIeuqVlQmV7YGbITCz5vAniTpSOIZsPcXUuKFdXwpXCR4NVmOF4XIYogjcW6R0pC e3xS7jYJizcQLzH4U1Bg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3tkhg623je-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 10 Oct 2023 15:01:18 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id E16A4100058; Tue, 10 Oct 2023 15:01:14 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D6E45231518; Tue, 10 Oct 2023 15:01:14 +0200 (CEST) Received: from localhost (10.201.20.32) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 10 Oct 2023 15:01:14 +0200 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v6 08/11] arm64: dts: st: add RIFSC as an access controller for STM32MP25x boards Date: Tue, 10 Oct 2023 14:57:16 +0200 Message-ID: <20231010125719.784627-9-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231010125719.784627-1-gatien.chevallier@foss.st.com> References: <20231010125719.784627-1-gatien.chevallier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.20.32] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-10_08,2023-10-10_01,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org RIFSC is a firewall controller. Change its compatible so that it matches the documentation and reference RIFSC as an access-control-provider. Signed-off-by: Gatien Chevallier --- Changes in V6: - Renamed access-controller to access-controllers - Removal of access-control-provider property Changes in V5: - Renamed feature-domain* to access-control* Changes in V2: - Fix rifsc node name - Move the "ranges" property under the "feature-domains" one arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 5268a4321841..f82318351dcd 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -105,11 +105,12 @@ soc@0 { interrupt-parent = <&intc>; ranges = <0x0 0x0 0x0 0x80000000>; - rifsc: rifsc-bus@42080000 { - compatible = "simple-bus"; + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc"; reg = <0x42080000 0x1000>; #address-cells = <1>; #size-cells = <1>; + #access-controller-cells = <1>; ranges; usart2: serial@400e0000 { @@ -117,6 +118,7 @@ usart2: serial@400e0000 { reg = <0x400e0000 0x400>; interrupts = ; clocks = <&ck_flexgen_08>; + access-controllers = <&rifsc 32>; status = "disabled"; }; };