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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/fsl-sec4.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP SEC4 Crypto Binding
+
+description:
+  CONTENTS
+    -Overview
+    -SEC 4 Node
+    -Job Ring Node
+    -Run Time Integrity Check (RTIC) Node
+    -Run Time Integrity Check (RTIC) Memory Node
+  NOTE, the SEC 4 is also known as Freescale's Cryptographic Accelerator
+  Accelerator and Assurance Module (CAAM).
+  For information on SEC4 SNVS, ref fsl-sec4-snvs.yaml
+
+  =====================================================================
+  Overview
+
+  DESCRIPTION
+
+  SEC 4 h/w can process requests from 2 types of sources.
+  1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
+  2. Job Rings (HW interface between cores & SEC 4 registers).
+
+  High Speed Data Path Configuration,
+
+  HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
+  such as the P4080.  The number of simultaneous dequeues the QI can make is
+  equal to the number of Descriptor Controller (DECO) engines in a particular
+  SEC version.  E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
+  dequeue from 5 subportals simultaneously.
+
+  Job Ring Data Path Configuration,
+
+  Each JR is located on a separate 4k page, they may (or may not) be made visible
+  in the memory partition devoted to a particular core.  The P4080 has 4 JRs, so
+  up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
+
+maintainers:
+  - Peng Fan <peng.fan@nxp.com>
+
+properties:
+  compatible:
+    enum:
+      - fsl,sec-v4.0
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+  ranges:
+    description:
+      A standard property. Specifies the physical address range of the SEC
+      4.0 register space (-SNVS not included).  A triplet that includes the
+      child address, parent address, & length.
+
+  interrupts:
+    description:
+      Specifies the interrupts generated by this device.  The value of the
+      interrupts property consists of one interrupt specifier. The format
+      of the specifier is defined by the binding document describing the
+      node's interrupt parent.
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+    maxItems: 4
+
+  clock-names:
+    oneOf:
+      - items:
+          - const: mem
+          - const: aclk
+          - const: ipg
+          - const: emi_slow
+      - items:
+          - const: aclk
+          - const: ipg
+      - items:
+          - const: ipg
+          - const: aclk
+          - const: mem
+
+  fsl,sec-era:
+    description:
+      Optional. A standard property. Define the 'ERA' of the SEC device.
+    $ref: /schemas/types.yaml#/definitions/uint32
+
+patternProperties:
+  "jr@[0-9a-f]+$":
+    type: object
+    description:
+      Child of the crypto node defines data processing interface to SEC 4
+      across the peripheral bus for purposes of processing
+      cryptographic descriptors. The specified address
+      range can be made visible to one (or more) cores.
+      The interrupt defined for this node is controlled within
+      the address range of this node.
+
+    properties:
+      compatible:
+        enum:
+          - fsl,sec-v4.0-job-ring
+
+      reg:
+        maxItems: 1
+
+      interrupts:
+        description:
+          Specifies the interrupts generated by this device.  The value of the
+          interrupts property consists of one interrupt specifier. The format
+          of the specifier is defined by the binding document describing the
+          node's interrupt parent.
+        maxItems: 1
+
+      fsl,liodn:
+        description:
+          Specifies the LIODN to be used in conjunction with the ppid-to-liodn
+          table that specifies the PPID to LIODN mapping. Needed if the PAMU
+          is used.  Value is a 12 bit value where value is a LIODN ID for this
+          JR. This property is normally set by boot firmware.
+        $ref: /schemas/types.yaml#/definitions/uint32-array
+        maximum: 0x1
+
+    required:
+      - compatible
+      - reg
+      - interrupts
+
+  "rtic@[0-9a-f]+$":
+    type: object
+    description:
+      Run Time Integrity Check (RTIC) Node. Child node of the crypto node.
+      Defines a register space that contains up to 5 sets of addresses and
+      their lengths (sizes) that will be checked at run time.  After an
+      initial hash result is calculated, these addresses are checked by HW
+      to monitor any change.  If any memory is modified, a Security Violation
+      is triggered (see SNVS definition).
+
+    properties:
+      compatible:
+        enum:
+          - fsl,sec-v4.0-rtic
+
+      "#address-cells":
+        const: 1
+
+      "#size-cells":
+        const: 1
+
+      reg:
+        minItems: 1
+        maxItems: 2
+
+      ranges:
+        description:
+          A standard property.  Specifies the physical address range of the
+          SEC 4 register space (-SNVS not included).  A triplet that includes
+          the child address, parent address, & length.
+
+    required:
+      - compatible
+      - reg
+      - "#address-cells"
+      - "#size-cells"
+      - ranges
+
+    patternProperties:
+      "rtic-[a-f]@[0-9]+$":
+        type: object
+        description:
+          Run Time Integrity Check (RTIC) Memory Node. A child node that
+          defines individual RTIC memory regions that are used to perform
+          run-time integrity check of memory areas that should not modified.
+          The node defines a register that contains the memory address &
+          length (combined) and a second register that contains the hash
+          result in big endian format.
+
+        properties:
+          compatible:
+            enum:
+              - fsl,sec-v4.0-rtic-memory
+
+          reg:
+            minItems: 1
+            maxItems: 2
+
+          fsl,rtic-region:
+            description:
+              Specifies the HW address (36 bit address) for this region
+              followed by the length of the HW partition to be checked;
+              the address is represented as a 64 bit quantity followed
+              by a 32 bit length.
+            $ref: /schemas/types.yaml#/definitions/uint32-array
+            minItems: 1
+            maxItems: 3
+
+          fsl,liodn:
+            description:
+              Specifies the LIODN to be used in conjunction with
+              the ppid-to-liodn table that specifies the PPID to LIODN
+              mapping.  Needed if the PAMU is used.  Value is a 12 bit value
+              where value is a LIODN ID for this RTIC memory region. This
+              property is normally set by boot firmware.
+            $ref: /schemas/types.yaml#/definitions/uint32-array
+            minItems: 1
+            maxItems: 3
+
+        required:
+          - compatible
+          - reg
+
+required:
+  - compatible
+  - reg
+
+unevaluatedProperties: false
+
+examples:
+  # iMX6QDL/SX requires four clocks
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/imx6qdl-clock.h>
+
+    crypto@300000 {
+        compatible = "fsl,sec-v4.0";
+        fsl,sec-era = <2>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        reg = <0x300000 0x10000>;
+        ranges = <0 0x300000 0x10000>;
+        interrupt-parent = <&mpic>;
+        interrupts = <92 2>;
+        clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
+                 <&clks IMX6QDL_CLK_CAAM_ACLK>,
+                 <&clks IMX6QDL_CLK_CAAM_IPG>,
+                 <&clks IMX6QDL_CLK_EIM_SLOW>;
+        clock-names = "mem", "aclk", "ipg", "emi_slow";
+
+        sec_jr0: jr@1000 {
+            compatible = "fsl,sec-v4.0-job-ring";
+            reg = <0x1000 0x1000>;
+            interrupt-parent = <&mpic>;
+            interrupts = <88 2>;
+        };
+
+        sec_jr1: jr@2000 {
+           compatible = "fsl,sec-v4.0-job-ring";
+           reg = <0x2000 0x1000>;
+           interrupt-parent = <&mpic>;
+           interrupts = <89 2>;
+        };
+
+        sec_jr2: jr@3000 {
+          compatible = "fsl,sec-v4.0-job-ring";
+          reg = <0x3000 0x1000>;
+          interrupt-parent = <&mpic>;
+          interrupts = <90 2>;
+        };
+
+        sec_jr3: jr@4000 {
+           compatible = "fsl,sec-v4.0-job-ring";
+           reg = <0x4000 0x1000>;
+           interrupt-parent = <&mpic>;
+           interrupts = <91 2>;
+        };
+
+        rtic@6000 {
+            compatible = "fsl,sec-v4.0-rtic";
+            #address-cells = <1>;
+            #size-cells = <1>;
+            reg = <0x6000 0x100>;
+            ranges = <0x0 0x6100 0xe00>;
+
+            rtic_a: rtic-a@0 {
+               compatible = "fsl,sec-v4.0-rtic-memory";
+               reg = <0x00 0x20 0x100 0x80>;
+            };
+
+            rtic_b: rtic-b@20 {
+                compatible = "fsl,sec-v4.0-rtic-memory";
+                reg = <0x20 0x20 0x200 0x80>;
+            };
+
+            rtic_c: rtic-c@40 {
+                compatible = "fsl,sec-v4.0-rtic-memory";
+                reg = <0x40 0x20 0x300 0x80>;
+            };
+
+            rtic_d: rtic-d@60 {
+                compatible = "fsl,sec-v4.0-rtic-memory";
+                reg = <0x60 0x20 0x500 0x80>;
+            };
+        };
+    };
+
+  # iMX6UL does only require three clocks
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/imx6ul-clock.h>
+
+    crypto: crypto@2140000 {
+        compatible = "fsl,sec-v4.0";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        reg = <0x2140000 0x3c000>;
+        ranges = <0 0x2140000 0x3c000>;
+        interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+
+        clocks = <&clks IMX6UL_CLK_CAAM_IPG>,
+                 <&clks IMX6UL_CLK_CAAM_ACLK>,
+                 <&clks IMX6UL_CLK_CAAM_MEM>;
+        clock-names = "ipg", "aclk", "mem";
+    };
+...
