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Fri, 17 Feb 2023 21:38:39 -0800 Received: from xhdharshah40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Fri, 17 Feb 2023 23:38:37 -0600 From: Harsha Harsha To: , , , , , CC: , , Harsha Harsha , Dhaval Shah Subject: [PATCH 2/4] firmware: xilinx: Add ZynqMP RSA API for RSA encrypt/decrypt operation Date: Sat, 18 Feb 2023 11:08:07 +0530 Message-ID: <20230218053809.1780-3-harsha.harsha@amd.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230218053809.1780-1-harsha.harsha@amd.com> References: <20230218053809.1780-1-harsha.harsha@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00010206:EE_|LV2PR12MB5847:EE_ X-MS-Office365-Filtering-Correlation-Id: b555a1b0-6e24-4009-e415-08db11726446 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nfaPsC2Q9R8l1I3gMnHcauFc8bdWoUbhWHNNPqKAVuaQaEbG85SdAI4m7iV7Y7HEx1fyOVvV+2XdRIrEme/Bo36NGeRaVQz6nWrYh7F0pgwT3JE0oSJNN2kWekhxxZBaOfijfcuYSLVukzULMduF6UMUh3FM8Fm5R97LaH7OmvZUhtf15OUeTy27ZFDRUSeMmFTZAevNUT1VAM0cPryzvo0HusXtk8X2AXh5C6YUv0HpAk3XcaXzSLLbU9ofqf57r+CnbvBSCGO2fBV9eioH5/4Kv251CwIZ6aHe50X1kZ9WE08NqTACFmomRryq91P/ZHXDrOcuQrV0cNt04Wv6MNSLO54a4+6A9qJBVL2U1Qlefgn+ILBbCPEmFogJqEGsq24zB//uG3QoMtaG0DmNA4jYpf1F5o45/9cM4Mc6Gmhe/xJFIS1pLN/Pax8W1wFLiGA7bhaeHHtIxzVx+4MVHkHxusudYemDyI0TRVD2kLX1wBDRWkCu4Ec7+IpgECNSAsN5AqvGy9KdV1W3BBLFzelSzwzV+v2MWIggO2xdzp+DC9utPeHz8Ju+jbEJ7ZpiPv7/JrGQeHhvfLKKOPM9V+UNnm95chDRSRNUjJsdH2SneFxLeS1pMvambuqBIQs8FywjS0VOVaWPzMa4nmBxun/H4dh+uyjnh1YXs971R0LUzfp9249Bx5tmNQCHxHoAo1h2em4TV6Fobbt/l1ERz56qnM97J8aIiEza+7CA0/nDydWuL3LdHJY2qmuc5+xF X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Signed-off-by: Harsha Harsha Co-developed-by: Dhaval Shah Signed-off-by: Dhaval Shah --- drivers/firmware/xilinx/zynqmp.c | 21 +++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++ 2 files changed, 29 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index 10ae42a2ae22..d6f73823bab4 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -1426,6 +1426,27 @@ int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags) } EXPORT_SYMBOL_GPL(zynqmp_pm_sha_hash); +/** + * zynqmp_pm_rsa - Access RSA hardware to encrypt/decrypt the data with RSA. + * @address: Address of the data + * @size: Size of the data. + * @flags: + * BIT(0) - Encryption/Decryption + * 0 - RSA decryption with private key + * 1 - RSA encryption with public key. + * + * Return: Returns status, either success or error code. + */ +int zynqmp_pm_rsa(const u64 address, const u32 size, const u32 flags) +{ + u32 lower_32_bits = lower_32_bits(address); + u32 upper_32_bits = upper_32_bits(address); + + return zynqmp_pm_invoke_fn(PM_SECURE_RSA, upper_32_bits, lower_32_bits, + size, flags, NULL); +} +EXPORT_SYMBOL_GPL(zynqmp_pm_rsa); + /** * zynqmp_pm_register_notifier() - PM API for register a subsystem * to be notified about specific diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index cd5acfa29cbc..8666b0c3cd66 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -117,6 +117,7 @@ enum pm_api_id { PM_FPGA_GET_STATUS = 23, PM_GET_CHIPID = 24, PM_SECURE_SHA = 26, + PM_SECURE_RSA = 27, PM_PINCTRL_REQUEST = 28, PM_PINCTRL_RELEASE = 29, PM_PINCTRL_GET_FUNCTION = 30, @@ -542,6 +543,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, const enum zynqmp_pm_request_ack ack); int zynqmp_pm_aes_engine(const u64 address, u32 *out); int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags); +int zynqmp_pm_rsa(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_get_status(u32 *value); int zynqmp_pm_write_ggs(u32 index, u32 value); @@ -744,6 +746,12 @@ static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size, return -ENODEV; } +static inline int zynqmp_pm_rsa(const u64 address, const u32 size, + const u32 flags) +{ + return -ENODEV; +} + static inline int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags) {