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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id o23-20020ac24e97000000b004867a427026sm458568lfr.40.2022.07.21.06.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Jul 2022 06:43:13 -0700 (PDT) From: Linus Walleij To: linux-crypto@vger.kernel.org, Herbert Xu , "David S . Miller" Cc: phone-devel@vger.kernel.org, Stefan Hansson , Linus Walleij Subject: [PATCH 13/15] crypto: ux500/hash: Use AMBA core primecell IDs Date: Thu, 21 Jul 2022 15:40:48 +0200 Message-Id: <20220721134050.1047866-14-linus.walleij@linaro.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220721134050.1047866-1-linus.walleij@linaro.org> References: <20220721134050.1047866-1-linus.walleij@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Use the AMBA (PrimeCell) bus core define and read 32bit CID and PID from the peripheral, then check those. Signed-off-by: Linus Walleij --- drivers/crypto/ux500/hash/hash_alg.h | 11 ++--------- drivers/crypto/ux500/hash/hash_core.c | 27 +++++++++++++++++++-------- 2 files changed, 21 insertions(+), 17 deletions(-) diff --git a/drivers/crypto/ux500/hash/hash_alg.h b/drivers/crypto/ux500/hash/hash_alg.h index cc44d3cb21ac..96c614444fa2 100644 --- a/drivers/crypto/ux500/hash/hash_alg.h +++ b/drivers/crypto/ux500/hash/hash_alg.h @@ -63,15 +63,8 @@ #define HASH_STR_NBLW_MASK 0x0000001FUL #define HASH_NBLW_MAX_VAL 0x1F -/* PrimeCell IDs */ -#define HASH_P_ID0 0xE0 -#define HASH_P_ID1 0x05 -#define HASH_P_ID2 0x38 -#define HASH_P_ID3 0x00 -#define HASH_CELL_ID0 0x0D -#define HASH_CELL_ID1 0xF0 -#define HASH_CELL_ID2 0x05 -#define HASH_CELL_ID3 0xB1 +/* PrimeCell ID */ +#define UX500_HASH_PID 0x003805E0U /* Hardware access method */ enum hash_mode { diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c index 83833cbe595f..a64edfb1cd96 100644 --- a/drivers/crypto/ux500/hash/hash_core.c +++ b/drivers/crypto/ux500/hash/hash_core.c @@ -13,6 +13,7 @@ #define pr_fmt(fmt) "hashX hashX: " fmt +#include #include #include #include @@ -940,18 +941,28 @@ int hash_check_hw(struct hash_device_data *device_data) unsigned int regs[] = { UX500_HASH_PERIPHID0, UX500_HASH_PERIPHID1, UX500_HASH_PERIPHID2, UX500_HASH_PERIPHID3, UX500_HASH_CELLID0, UX500_HASH_CELLID1, UX500_HASH_CELLID2, UX500_HASH_CELLID3 }; - unsigned int expected[] = { HASH_P_ID0, HASH_P_ID1, HASH_P_ID2, HASH_P_ID3, - HASH_CELL_ID0, HASH_CELL_ID1, HASH_CELL_ID2, HASH_CELL_ID3 }; unsigned int val; + u32 pid; + u32 cid; int i; - for (i = 0; i < ARRAY_SIZE(regs); i++) { + for (pid = 0, i = 0; i < 8; i++) { regmap_read(device_data->map, regs[i], &val); - if (val != expected[i]) { - dev_err(device_data->dev, "ID word %d was %08x expected %08x\n", - i, val, expected[i]); - return -ENODEV; - } + if (i < 4) + pid |= (val & 255) << (i * 8); + else + cid |= (val & 255) << ((i - 4) * 8); + } + + if (cid != AMBA_CID) { + dev_err(device_data->dev, "AMBA CID was %08x expected %08x\n", + cid, AMBA_CID); + return -ENODEV; + } + if (pid != UX500_HASH_PID) { + dev_err(device_data->dev, "PID was %08x expected %08x\n", + pid, UX500_HASH_PID); + return -ENODEV; } return 0;