From patchwork Mon Jan 17 11:07:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 532957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01207C4167D for ; Mon, 17 Jan 2022 11:06:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238873AbiAQLGz (ORCPT ); Mon, 17 Jan 2022 06:06:55 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:25926 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238961AbiAQLGj (ORCPT ); Mon, 17 Jan 2022 06:06:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1642417600; x=1673953600; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lpP0lJkn+kaM0L/dSWda42EaX0finN6iz9h/n2ezhV4=; b=c2HbDpqPJN9BVnb6Yy71VM6reT2hYNSSAwFZh+ICtW9VVMRODnAxb0Zn VzZRTW/fuN17+jWd6ybdG70n6dmabJK5k/EqX1lcxkSGjF4q2kkToenYe voFvpM/7wdqTusF4+eoiojJbwxUBCCifpXzRtQNoDTsK5I4CTh6CQSdbK 4gJ00DflI2OS1sVVvmInmWTr26IkP/h87sVlKHMDkSeMHhdmTnXX/AySL 89vGPAocxzhNwTFGPy5Z2snNHxqVyKs7/U01VZKIYWiZeE4CEU9HC4KJq PD6rT1j3W4h6jlZlEEMc//paDqBr7NBuPIoFkf7Ag92kB2oI1ysFqIdu4 Q==; IronPort-SDR: UPWG/TkFqAVmK/OQhSiZm2kwsVkz3r/aFWDzsMOvcYDCJvzIxkvWSPM//plH9+7tK/RX342ib3 AA1/NHh505sTgfqittMM3Q4mimHDE4Z5DVIkpELQNiYaZWOGg46wSaaesadow1nqsWU0utgLJw JM/dNIrsPOyt6o9HIUnJO7xsgK5Sp7WT+UZh+phvyPu37TXyC1DezlM/bKl1RFvFGTYe1mOJZp K/f5YyY0FNrxt5gXF3sjQ+MICve3iEz4/9b8o0HzG+xMYwWn8LPHcbOulCcPbGzxglYEsRoxs8 A0u3/0c2U95alEivP17ksrcR X-IronPort-AV: E=Sophos;i="5.88,295,1635231600"; d="scan'208";a="149870616" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Jan 2022 04:06:39 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.87.72) by chn-vm-ex02.mchp-main.com (10.10.87.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 17 Jan 2022 04:06:29 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 17 Jan 2022 04:06:24 -0700 From: To: , , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v4 06/14] dt-bindings: spi: add bindings for microchip mpfs spi Date: Mon, 17 Jan 2022 11:07:47 +0000 Message-ID: <20220117110755.3433142-7-conor.dooley@microchip.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220117110755.3433142-1-conor.dooley@microchip.com> References: <20220117110755.3433142-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Conor Dooley Add device tree bindings for the {q,}spi controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley Reviewed-by: Rob Herring --- .../bindings/spi/microchip,mpfs-spi.yaml | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml new file mode 100644 index 000000000000..ece261b8e963 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings + +maintainers: + - Conor Dooley + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + enum: + - microchip,mpfs-spi + - microchip,mpfs-qspi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" + spi@20108000 { + compatible = "microchip,mpfs-spi"; + reg = <0x20108000 0x1000>; + clocks = <&clkcfg CLK_SPI0>; + interrupt-parent = <&plic>; + interrupts = <54>; + spi-max-frequency = <25000000>; + }; +...