From patchwork Mon Jul 26 07:14:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 485943 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D2E8C19F36 for ; Mon, 26 Jul 2021 07:17:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3C08C60F45 for ; Mon, 26 Jul 2021 07:17:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232347AbhGZGhA (ORCPT ); Mon, 26 Jul 2021 02:37:00 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:56688 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S232307AbhGZGg7 (ORCPT ); Mon, 26 Jul 2021 02:36:59 -0400 X-UUID: 47b170a8835d494498e0fb4f6ea05f59-20210726 X-UUID: 47b170a8835d494498e0fb4f6ea05f59-20210726 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1103810837; Mon, 26 Jul 2021 15:17:26 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 26 Jul 2021 15:17:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 26 Jul 2021 15:17:24 +0800 From: Sam Shih To: Rob Herring , Sean Wang , Linus Walleij , Matthias Brugger , Matt Mackall , Herbert Xu , Greg Kroah-Hartman , Wim Van Sebroeck , Guenter Roeck , Michael Turquette , Stephen Boyd , Hsin-Yi Wang , Enric Balletbo i Serra , Fabien Parent , Seiya Wang , , , , , , , , , CC: John Crispin , Ryder Lee , Sam Shih Subject: [PATCH 04/12] pinctrl: mediatek: moore: use pin number in mtk_pin_desc instead of array index Date: Mon, 26 Jul 2021 15:14:31 +0800 Message-ID: <20210726071439.14248-5-sam.shih@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210726071439.14248-1-sam.shih@mediatek.com> References: <20210726071439.14248-1-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Certain SoC are missing the middle part gpios in consecutive pins, it's better to use pin number in mtk_pin_desc instead of array index for the extensibility Signed-off-by: Sam Shih --- drivers/pinctrl/mediatek/pinctrl-moore.c | 61 ++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 3a4a23c40a71..16206254ec3d 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -35,6 +35,19 @@ static const struct pin_config_item mtk_conf_items[] = { }; #endif +static int mtk_pin_desc_lookup(struct mtk_pinctrl *hw, int pin) +{ + int idx; + + for (idx = 0 ; idx < hw->soc->npins ; idx++) + if (hw->soc->pins[idx].number == pin) + break; + if (idx < hw->soc->npins) + return idx; + + return -EINVAL; +} + static int mtk_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, unsigned int group) { @@ -74,6 +87,13 @@ static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, { struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); const struct mtk_pin_desc *desc; + int err; + + err = mtk_pin_desc_lookup(hw, pin); + if (err >= 0) + pin = err; + else + return err; desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; @@ -87,6 +107,13 @@ static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev, { struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); const struct mtk_pin_desc *desc; + int err; + + err = mtk_pin_desc_lookup(hw, pin); + if (err >= 0) + pin = err; + else + return err; desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; @@ -102,6 +129,12 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, int val, val2, err, reg, ret = 1; const struct mtk_pin_desc *desc; + err = mtk_pin_desc_lookup(hw, pin); + if (err >= 0) + pin = err; + else + return err; + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; switch (param) { @@ -217,6 +250,12 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, u32 reg, param, arg; int cfg, err = 0; + err = mtk_pin_desc_lookup(hw, pin); + if (err >= 0) + pin = err; + else + return err; + desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; for (cfg = 0; cfg < num_configs; cfg++) { @@ -434,6 +473,12 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) const struct mtk_pin_desc *desc; int value, err; + err = mtk_pin_desc_lookup(hw, gpio); + if (err >= 0) + gpio = err; + else + return err; + desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); @@ -447,6 +492,15 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) { struct mtk_pinctrl *hw = gpiochip_get_data(chip); const struct mtk_pin_desc *desc; + int err; + + err = mtk_pin_desc_lookup(hw, gpio); + if (err >= 0) { + gpio = err; + } else { + dev_err(hw->dev, "Failed to set gpio %d\n", gpio); + return; + } desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; @@ -488,6 +542,13 @@ static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset, struct mtk_pinctrl *hw = gpiochip_get_data(chip); const struct mtk_pin_desc *desc; u32 debounce; + int err; + + err = mtk_pin_desc_lookup(hw, offset); + if (err >= 0) + offset = err; + else + return err; desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];