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[92.34.204.253]) by smtp.gmail.com with ESMTPSA id m4sm3699740ljc.20.2021.05.11.06.29.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 May 2021 06:29:35 -0700 (PDT) From: Linus Walleij To: Matt Mackall , Herbert Xu , Deepak Saxena Cc: linux-crypto@vger.kernel.org, Arnd Bergmann , Linus Walleij Subject: [PATCH 1/5] hw_random: ixp4xx: enable compile-testing Date: Tue, 11 May 2021 15:29:24 +0200 Message-Id: <20210511132928.814697-1-linus.walleij@linaro.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Arnd Bergmann The driver is almost portable already, it just needs to include the new header for the cpu definition. Cc: Deepak Saxena Signed-off-by: Arnd Bergmann Signed-off-by: Linus Walleij --- The idea is to apply this through the ARM SoC tree along with other IXP4xx refactorings. Please tell me if you prefer another solution. --- drivers/char/hw_random/Kconfig | 2 +- drivers/char/hw_random/ixp4xx-rng.c | 3 +-- 2 files changed, 2 insertions(+), 3 deletions(-) -- 2.30.2 Acked-by: Herbert Xu diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index 1fe006f3f12f..f033a11cc90d 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -152,7 +152,7 @@ config HW_RANDOM_VIA config HW_RANDOM_IXP4XX tristate "Intel IXP4xx NPU HW Pseudo-Random Number Generator support" - depends on ARCH_IXP4XX + depends on ARCH_IXP4XX || COMPILE_TEST default HW_RANDOM help This driver provides kernel-side support for the Pseudo-Random diff --git a/drivers/char/hw_random/ixp4xx-rng.c b/drivers/char/hw_random/ixp4xx-rng.c index beec1627db3c..34781028caec 100644 --- a/drivers/char/hw_random/ixp4xx-rng.c +++ b/drivers/char/hw_random/ixp4xx-rng.c @@ -21,10 +21,9 @@ #include #include #include +#include #include -#include - static int ixp4xx_rng_data_read(struct hwrng *rng, u32 *buffer) {