From patchwork Thu Dec 10 20:03:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Herring X-Patchwork-Id: 341068 Delivered-To: patch@linaro.org Received: by 2002:a02:85a7:0:0:0:0:0 with SMTP id d36csp5860072jai; Thu, 10 Dec 2020 12:05:34 -0800 (PST) X-Google-Smtp-Source: ABdhPJyD/pTeybKGcmkDHUcJxjKXCCKYma4KtL+AmAhxLxIafuqvd+TYC6Qs1rN6eUCNqz8rdwrr X-Received: by 2002:aa7:cf8f:: with SMTP id z15mr8530709edx.17.1607630734490; Thu, 10 Dec 2020 12:05:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1607630734; cv=none; d=google.com; s=arc-20160816; b=OTGr4DkOVpY7JFODvF6Pee+tlkDXtJBADzxb/0J+C2e1VRaLaJfxdiDD5LwgyAflCb PctcAwYL8oQwqdDUxjM18Up0GlbGZVvtNMr6xNunA5m+YX4xFCaTEn0gFXiI0m/n2A9V DKvmKLIGAU6TTjg5TVlcs7wh/P/mpgEpt0N9OK3eOdIKyYmP7RHKnllCbewnthY7+lw3 b7NKrOHnQT+DJlTyffuI2VYDtajp9ETyk6/nR5RIjk9ujpfex/fy9UfgvDwCA3Dia2o0 gupIcGRS4cLUfS9WN1f7MDOeZ2foeANPZcoTOxmYUmOoWDcu11kNGLKXrGyht4NBeLwp UplQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=wYT6D6yOTVKMl9lCBQT5EHKzZ4TTN7Y8gqIdAhxWbzU=; b=zeTwoCeaNxvWObsxd3xgGywfIg/SF4PztfPtKCEDK1kGFdr+sXAqDGhwn9spDE0/Vi 3CICSucLs/b8OmlacPbMA7WPNupUwvHDUKnpsOxYFIUtB0ioT6rNzx3BJr7prlUMuNQh TxDQWObxWKtk5qTOtKUBpNupP/75ng53DmO+g4Sb1RaiMWsSBUOWyhCUnhWXsV8d4VAA bcayZ17NjKhQWlT55BwEodsEQM6T/y+Hvt0fPguF16YS9JTyJg82QB4G7YY6cxwY+Yco 23PBkvfKI+UJIjETT6rIxUMFkOKgJxU/3gWDJxw0WfcgLfs9M2C77OQ7bU9Q6AZwEVU/ jy3A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [23.128.96.18]) by mx.google.com with ESMTP id a2si3094758ejp.666.2020.12.10.12.05.34; Thu, 10 Dec 2020 12:05:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) client-ip=23.128.96.18; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-crypto-owner@vger.kernel.org designates 23.128.96.18 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404567AbgLJUEL (ORCPT + 2 others); Thu, 10 Dec 2020 15:04:11 -0500 Received: from mail-oi1-f193.google.com ([209.85.167.193]:45608 "EHLO mail-oi1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404559AbgLJUEG (ORCPT ); Thu, 10 Dec 2020 15:04:06 -0500 Received: by mail-oi1-f193.google.com with SMTP id f132so7103513oib.12; Thu, 10 Dec 2020 12:03:50 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wYT6D6yOTVKMl9lCBQT5EHKzZ4TTN7Y8gqIdAhxWbzU=; b=lXfSDT+B816vq7GPV5aNcidW2P4KOPoR38uMftCfGU6WQuMQ4z+Jtn8kNVMJ8nQ1at xT6hbWbX3LbAY1JLClOmbM9Zc966gLh+7DrM0Yv98RmLr+3WvDFNd3s2+oCZoHb7i3dk ORgUI/zvyYjPl3FQlDasHh2xJYiVm59zlxm4uTqQbLjoX0dbEKyQP8cniT4nbBG734IO uLl7gFgtOu4bxOcsLKMwXANdNVMfWNQv/ndGrjpj51Ik6FeCy+39qJpGuuJY/5DUcA8i jX8P2e2BpP876xdrfK9Cq/fpDMsPjuzrIxuJBFydpPTBz4Jus9pGb5mByk+1AGmmMxBA m4lg== X-Gm-Message-State: AOAM532K9G/3qvCTKv4Xt+5yAhEiPFZgDIWvR/1Qa779NIpgQxgHBt/S AK+6nnB3lXMPl1c/8zgJAA== X-Received: by 2002:aca:2418:: with SMTP id n24mr6393172oic.62.1607630604964; Thu, 10 Dec 2020 12:03:24 -0800 (PST) Received: from xps15.herring.priv (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.googlemail.com with ESMTPSA id o82sm1220636oih.5.2020.12.10.12.03.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Dec 2020 12:03:23 -0800 (PST) From: Rob Herring To: Jamie Iles , Herbert Xu , "David S. Miller" , soc@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 4/4] dt-bindings: Remove PicoXcell bindings Date: Thu, 10 Dec 2020 14:03:15 -0600 Message-Id: <20201210200315.2965567-5-robh@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201210200315.2965567-1-robh@kernel.org> References: <20201210200315.2965567-1-robh@kernel.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org PicoXcell has had nothing but treewide cleanups for at least the last 8 years and no signs of activity. The most recent activity is a yocto vendor kernel based on v3.0 in 2015. Cc: Jamie Iles Cc: linux-crypto@vger.kernel.org Signed-off-by: Rob Herring --- I'll take this via the DT tree. .../devicetree/bindings/arm/picoxcell.txt | 24 ------------------- .../bindings/crypto/picochip-spacc.txt | 21 ---------------- .../devicetree/bindings/net/macb.txt | 2 -- .../bindings/timer/snps,dw-apb-timer.yaml | 7 ------ 4 files changed, 54 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/picoxcell.txt delete mode 100644 Documentation/devicetree/bindings/crypto/picochip-spacc.txt -- 2.25.1 diff --git a/Documentation/devicetree/bindings/arm/picoxcell.txt b/Documentation/devicetree/bindings/arm/picoxcell.txt deleted file mode 100644 index e75c0ef51e69..000000000000 --- a/Documentation/devicetree/bindings/arm/picoxcell.txt +++ /dev/null @@ -1,24 +0,0 @@ -Picochip picoXcell device tree bindings. -======================================== - -Required root node properties: - - compatible: - - "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device. - - "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device. - - "picochip,pc3x3" : picoXcell PC3X3 device based board. - - "picochip,pc3x2" : picoXcell PC3X2 device based board. - -Timers required properties: - - compatible = "picochip,pc3x2-timer" - - interrupts : The single IRQ line for the timer. - - clock-freq : The frequency in HZ of the timer. - - reg : The register bank for the timer. - -Note: two timers are required - one for the scheduler clock and one for the -event tick/NOHZ. - -VIC required properties: - - compatible = "arm,pl192-vic". - - interrupt-controller. - - reg : The register bank for the device. - - #interrupt-cells : Must be 1. diff --git a/Documentation/devicetree/bindings/crypto/picochip-spacc.txt b/Documentation/devicetree/bindings/crypto/picochip-spacc.txt deleted file mode 100644 index df1151f87745..000000000000 --- a/Documentation/devicetree/bindings/crypto/picochip-spacc.txt +++ /dev/null @@ -1,21 +0,0 @@ -Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings - -Picochip picoXcell devices contain crypto offload engines that may be used for -IPSEC and femtocell layer 2 ciphering. - -Required properties: - - compatible : "picochip,spacc-ipsec" for the IPSEC offload engine - "picochip,spacc-l2" for the femtocell layer 2 ciphering engine. - - reg : Offset and length of the register set for this device - - interrupts : The interrupt line from the SPAcc. - - ref-clock : The input clock that drives the SPAcc. - -Example SPAcc node: - -spacc@10000 { - compatible = "picochip,spacc-ipsec"; - reg = <0x100000 0x10000>; - interrupt-parent = <&vic0>; - interrupts = <24>; - ref-clock = <&ipsec_clk>, "ref"; -}; diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt index 0b61a90f1592..46dc52c0739a 100644 --- a/Documentation/devicetree/bindings/net/macb.txt +++ b/Documentation/devicetree/bindings/net/macb.txt @@ -7,8 +7,6 @@ Required properties: Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC. Use "cdns,np4-macb" for NP4 SoC devices. Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb". - Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on - the Cadence GEM, or the generic form: "cdns,gem". Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs. Use "atmel,sama5d3-macb" for the 10/100Mbit IP available on Atmel sama5d3 SoCs. Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs. diff --git a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml index 2fc617377e2c..d65faf289a83 100644 --- a/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml +++ b/Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml @@ -38,13 +38,6 @@ properties: clock-frequency: true - clock-freq: - $ref: "/schemas/types.yaml#/definitions/uint32" - description: | - Has the same meaning as the 'clock-frequency' property - timer clock - frequency in HZ, but is defined only for the backwards compatibility - with the picoxcell platform. - additionalProperties: false required: