diff mbox series

[12/32] crypto: qat - loader: remove global CSRs helpers

Message ID 20201106112810.2566-13-jack.xu@intel.com
State Accepted
Commit 8f87b6271ec85c09af6406665324c74bb79e3216
Headers show
Series crypto: qat - rework firmware loader in preparation for qat_4xxx | expand

Commit Message

Jack Xu Nov. 6, 2020, 11:27 a.m. UTC 
Include the offset of GLOBAL_CSR directly into the enum hal_global_csr
and remove the macros SET_GLB_CSR/GET_GLB_CSR to simplify the global CSR
access.

Signed-off-by: Jack Xu <jack.xu@intel.com>
Co-developed-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Signed-off-by: Wojciech Ziemba <wojciech.ziemba@intel.com>
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
---
 drivers/crypto/qat/qat_common/icp_qat_hal.h |  9 +++------
 drivers/crypto/qat/qat_common/qat_hal.c     | 20 ++++++++++----------
 2 files changed, 13 insertions(+), 16 deletions(-)
diff mbox series

Patch

diff --git a/drivers/crypto/qat/qat_common/icp_qat_hal.h b/drivers/crypto/qat/qat_common/icp_qat_hal.h
index 5640bb278bb1..c2166dacdf5b 100644
--- a/drivers/crypto/qat/qat_common/icp_qat_hal.h
+++ b/drivers/crypto/qat/qat_common/icp_qat_hal.h
@@ -5,9 +5,9 @@ 
 #include "icp_qat_fw_loader_handle.h"
 
 enum hal_global_csr {
-	MISC_CONTROL = 0x04,
-	ICP_RESET = 0x0c,
-	ICP_GLOBAL_CLK_ENABLE = 0x50
+	MISC_CONTROL = 0xA04,
+	ICP_RESET = 0xA0c,
+	ICP_GLOBAL_CLK_ENABLE = 0xA50
 };
 
 enum hal_ae_csr {
@@ -78,7 +78,6 @@  enum fcu_sts {
 #define XCWE_VOLUNTARY              (0x1)
 #define LCS_STATUS          (0x1)
 #define MMC_SHARE_CS_BITPOS         2
-#define GLOBAL_CSR                0xA00
 #define FCU_CTRL_AE_POS     0x8
 #define FCU_AUTH_STS_MASK   0x7
 #define FCU_STS_DONE_POS    0x9
@@ -91,8 +90,6 @@  enum fcu_sts {
 	ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)
 #define GET_CAP_CSR(handle, csr) \
 	ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)
-#define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val)
-#define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr)
 #define AE_CSR(handle, ae) \
 	((char __iomem *)(handle)->hal_cap_ae_local_csr_addr_v + ((ae) << 12))
 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr)))
diff --git a/drivers/crypto/qat/qat_common/qat_hal.c b/drivers/crypto/qat/qat_common/qat_hal.c
index f127233eec17..15ebb57ea14a 100644
--- a/drivers/crypto/qat/qat_common/qat_hal.c
+++ b/drivers/crypto/qat/qat_common/qat_hal.c
@@ -273,10 +273,10 @@  void qat_hal_reset(struct icp_qat_fw_loader_handle *handle)
 {
 	unsigned int ae_reset_csr;
 
-	ae_reset_csr = GET_GLB_CSR(handle, ICP_RESET);
+	ae_reset_csr = GET_CAP_CSR(handle, ICP_RESET);
 	ae_reset_csr |= handle->hal_handle->ae_mask << RST_CSR_AE_LSB;
 	ae_reset_csr |= handle->hal_handle->slice_mask << RST_CSR_QAT_LSB;
-	SET_GLB_CSR(handle, ICP_RESET, ae_reset_csr);
+	SET_CAP_CSR(handle, ICP_RESET, ae_reset_csr);
 }
 
 static void qat_hal_wr_indr_csr(struct icp_qat_fw_loader_handle *handle,
@@ -390,9 +390,9 @@  static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle)
 	unsigned char ae;
 
 	/* stop the timestamp timers */
-	misc_ctl = GET_GLB_CSR(handle, MISC_CONTROL);
+	misc_ctl = GET_CAP_CSR(handle, MISC_CONTROL);
 	if (misc_ctl & MC_TIMESTAMP_ENABLE)
-		SET_GLB_CSR(handle, MISC_CONTROL, misc_ctl &
+		SET_CAP_CSR(handle, MISC_CONTROL, misc_ctl &
 			    (~MC_TIMESTAMP_ENABLE));
 
 	for_each_set_bit(ae, &ae_mask, handle->hal_handle->ae_max_num) {
@@ -400,7 +400,7 @@  static void qat_hal_reset_timestamp(struct icp_qat_fw_loader_handle *handle)
 		qat_hal_wr_ae_csr(handle, ae, TIMESTAMP_HIGH, 0);
 	}
 	/* start timestamp timers */
-	SET_GLB_CSR(handle, MISC_CONTROL, misc_ctl | MC_TIMESTAMP_ENABLE);
+	SET_CAP_CSR(handle, MISC_CONTROL, misc_ctl | MC_TIMESTAMP_ENABLE);
 }
 
 #define ESRAM_AUTO_TINIT	BIT(2)
@@ -448,21 +448,21 @@  int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle)
 	unsigned int csr;
 
 	/* write to the reset csr */
-	ae_reset_csr = GET_GLB_CSR(handle, ICP_RESET);
+	ae_reset_csr = GET_CAP_CSR(handle, ICP_RESET);
 	ae_reset_csr &= ~(handle->hal_handle->ae_mask << RST_CSR_AE_LSB);
 	ae_reset_csr &= ~(handle->hal_handle->slice_mask << RST_CSR_QAT_LSB);
 	do {
-		SET_GLB_CSR(handle, ICP_RESET, ae_reset_csr);
+		SET_CAP_CSR(handle, ICP_RESET, ae_reset_csr);
 		if (!(times--))
 			goto out_err;
-		csr = GET_GLB_CSR(handle, ICP_RESET);
+		csr = GET_CAP_CSR(handle, ICP_RESET);
 	} while ((handle->hal_handle->ae_mask |
 		 (handle->hal_handle->slice_mask << RST_CSR_QAT_LSB)) & csr);
 	/* enable clock */
-	clk_csr = GET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE);
+	clk_csr = GET_CAP_CSR(handle, ICP_GLOBAL_CLK_ENABLE);
 	clk_csr |= handle->hal_handle->ae_mask << 0;
 	clk_csr |= handle->hal_handle->slice_mask << 20;
-	SET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE, clk_csr);
+	SET_CAP_CSR(handle, ICP_GLOBAL_CLK_ENABLE, clk_csr);
 	if (qat_hal_check_ae_alive(handle))
 		goto out_err;