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[209.132.180.67]) by mx.google.com with ESMTP id f66-v6si5264259pgc.391.2018.04.30.09.18.48; Mon, 30 Apr 2018 09:18:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=H8qZ/2Lq; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754555AbeD3QSs (ORCPT + 1 other); Mon, 30 Apr 2018 12:18:48 -0400 Received: from mail-wr0-f196.google.com ([209.85.128.196]:44147 "EHLO mail-wr0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753334AbeD3QSr (ORCPT ); Mon, 30 Apr 2018 12:18:47 -0400 Received: by mail-wr0-f196.google.com with SMTP id o15-v6so8576440wro.11 for ; Mon, 30 Apr 2018 09:18:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=lcnypoy5h+AqrQvMvZmSK8KhkPa+m+lRmvG+TuuFmwE=; b=H8qZ/2Lqd0t5ycvwoJPlkb9wZ3L8uQDqV4qKM3EhblnBjJoar+FgqktZ7LKj1zOERt qDBXjJilmiIwl3SvPwHNeJDzpUR1xSymyAQY0x7Jzs2IBiU7cr/R0W4I3uOtjzfNzGT/ /GMDKjiLag1S3SuWsZvACoH1+SOmNFotePMqw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=lcnypoy5h+AqrQvMvZmSK8KhkPa+m+lRmvG+TuuFmwE=; b=Kijsel2GyyJ0MyRdTFXzkrduAN+dw6AK7NcJmJYVberGQBfyY42iinMke3+XbtDPP4 I0kLHutcU7/J67tGJQtkVvEMyVT9Qp2xmz7x0IVYv21wp0aD1RkHX1Sp0f4og/bbj643 a+bEJKU0dPCQ5vJxAcVaAwR2JaVhcz6d/NxBrzhAQJfRYxY+EJLhtEFrlM8HbHqU3Wnu EFEdTNEzZDUnPKjr6JRWPJWkw7US24GG9JghOIIQB5J13bbD6YKCtDTlNQJMB3XjzVdH 7xF3RxsAukFytY5fzb9xn3p0FbR6LpYY/FM7FdBsQQF/5uubJhQ88pTHSFoMKwmzy84L 9h9w== X-Gm-Message-State: ALQs6tBTi+SEDGpNqgmo22haegeYnkexzgsdM8Ad/z+YJz8md2OVbO9I rdimMswmnjFljLdZ/cefWLAueP3vp9U= X-Received: by 2002:adf:9a27:: with SMTP id z36-v6mr8843321wrb.47.1525105125913; Mon, 30 Apr 2018 09:18:45 -0700 (PDT) Received: from localhost.localdomain ([2a01:e35:3995:5470:200:1aff:fe1b:b328]) by smtp.gmail.com with ESMTPSA id l1-v6sm5753845wre.54.2018.04.30.09.18.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 30 Apr 2018 09:18:45 -0700 (PDT) From: Ard Biesheuvel To: linux-crypto@vger.kernel.org, herbert@gondor.apana.org.au Cc: linux-arm-kernel@lists.infradead.org, dave.martin@arm.com, will.deacon@arm.com, Ard Biesheuvel Subject: [PATCH resend 02/10] crypto: arm64/sha2-ce - yield NEON after every block of input Date: Mon, 30 Apr 2018 18:18:22 +0200 Message-Id: <20180430161830.14892-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180430161830.14892-1-ard.biesheuvel@linaro.org> References: <20180430161830.14892-1-ard.biesheuvel@linaro.org> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Avoid excessive scheduling delays under a preemptible kernel by yielding the NEON after every block of input. Signed-off-by: Ard Biesheuvel --- arch/arm64/crypto/sha2-ce-core.S | 37 ++++++++++++++------ 1 file changed, 26 insertions(+), 11 deletions(-) -- 2.17.0 diff --git a/arch/arm64/crypto/sha2-ce-core.S b/arch/arm64/crypto/sha2-ce-core.S index 4c3c89b812ce..cd8b36412469 100644 --- a/arch/arm64/crypto/sha2-ce-core.S +++ b/arch/arm64/crypto/sha2-ce-core.S @@ -79,30 +79,36 @@ */ .text ENTRY(sha2_ce_transform) + frame_push 3 + + mov x19, x0 + mov x20, x1 + mov x21, x2 + /* load round constants */ - adr_l x8, .Lsha2_rcon +0: adr_l x8, .Lsha2_rcon ld1 { v0.4s- v3.4s}, [x8], #64 ld1 { v4.4s- v7.4s}, [x8], #64 ld1 { v8.4s-v11.4s}, [x8], #64 ld1 {v12.4s-v15.4s}, [x8] /* load state */ - ld1 {dgav.4s, dgbv.4s}, [x0] + ld1 {dgav.4s, dgbv.4s}, [x19] /* load sha256_ce_state::finalize */ ldr_l w4, sha256_ce_offsetof_finalize, x4 - ldr w4, [x0, x4] + ldr w4, [x19, x4] /* load input */ -0: ld1 {v16.4s-v19.4s}, [x1], #64 - sub w2, w2, #1 +1: ld1 {v16.4s-v19.4s}, [x20], #64 + sub w21, w21, #1 CPU_LE( rev32 v16.16b, v16.16b ) CPU_LE( rev32 v17.16b, v17.16b ) CPU_LE( rev32 v18.16b, v18.16b ) CPU_LE( rev32 v19.16b, v19.16b ) -1: add t0.4s, v16.4s, v0.4s +2: add t0.4s, v16.4s, v0.4s mov dg0v.16b, dgav.16b mov dg1v.16b, dgbv.16b @@ -131,16 +137,24 @@ CPU_LE( rev32 v19.16b, v19.16b ) add dgbv.4s, dgbv.4s, dg1v.4s /* handled all input blocks? */ - cbnz w2, 0b + cbz w21, 3f + + if_will_cond_yield_neon + st1 {dgav.4s, dgbv.4s}, [x19] + do_cond_yield_neon + b 0b + endif_yield_neon + + b 1b /* * Final block: add padding and total bit count. * Skip if the input size was not a round multiple of the block size, * the padding is handled by the C code in that case. */ - cbz x4, 3f +3: cbz x4, 4f ldr_l w4, sha256_ce_offsetof_count, x4 - ldr x4, [x0, x4] + ldr x4, [x19, x4] movi v17.2d, #0 mov x8, #0x80000000 movi v18.2d, #0 @@ -149,9 +163,10 @@ CPU_LE( rev32 v19.16b, v19.16b ) mov x4, #0 mov v19.d[0], xzr mov v19.d[1], x7 - b 1b + b 2b /* store new state */ -3: st1 {dgav.4s, dgbv.4s}, [x0] +4: st1 {dgav.4s, dgbv.4s}, [x19] + frame_pop ret ENDPROC(sha2_ce_transform)