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[209.132.180.67]) by mx.google.com with ESMTP id q16si2824191pfg.221.2018.03.10.07.23.41; Sat, 10 Mar 2018 07:23:41 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LZA0zeTa; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932377AbeCJPXj (ORCPT + 1 other); Sat, 10 Mar 2018 10:23:39 -0500 Received: from mail-wr0-f193.google.com ([209.85.128.193]:46452 "EHLO mail-wr0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932371AbeCJPXf (ORCPT ); Sat, 10 Mar 2018 10:23:35 -0500 Received: by mail-wr0-f193.google.com with SMTP id m12so11623400wrm.13 for ; Sat, 10 Mar 2018 07:23:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ofS9x65hNsKG4NHlkc24PsKWPCSGqKtHPcQzarX2eaU=; b=LZA0zeTaCF7Liv7CYrUqn7J3qn6gm+QjCh/9WHSNwu92ZPx6TwtPqcZVs/7oxjvapX YXWdTsa/HOqyPh4tIzOLOhZ0KDBGIEBvZTui69RoXWfYsqsBuzymMxQluqozi2VelsYo F96HozacOAHn9PgRaRkP5fmC5afm+wegAwRR8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ofS9x65hNsKG4NHlkc24PsKWPCSGqKtHPcQzarX2eaU=; b=QugINkWN2X+BymXft2nLqGTTAstogFI8BVhsuEg6IdnphrKaYu4z0/GzhDbcZFBheU SCBo9rENbLJcjU/TIK02KoRYy4Mc/QzeA9DCU873VhI1b8PDOIajSQOiAhWWoT4kg1+k acafcfXoPmIBtacSSI8Kh/oNvnFM8HY14FH7DgDOIuBIlwIbMhWaAdHGfvcHtPW99M6E 2jPlycM2knyX+QskkQ6YGsf+Fe1vmmx15o/rshxM+JdpP2cnGzJPzcpCs/6+dUgTCMSU LzeSOfIABneGSHB1Mph+grJ/wGBKUGLImjgPMldKdBxN+zBl/gVccPkGZUBY2opE8ldB P8Jw== X-Gm-Message-State: AElRT7HBQQ8NlfBixFfdQg6Nro4e/JqZ/RNzH7NMPxZ33XBod5xtO0kV shN4HZFXhS4Htk3i9CJI7mlOZYtLMZk= X-Received: by 10.223.142.173 with SMTP id q42mr1940750wrb.254.1520695414353; Sat, 10 Mar 2018 07:23:34 -0800 (PST) Received: from localhost.localdomain ([105.148.128.186]) by smtp.gmail.com with ESMTPSA id m9sm7027531wrf.13.2018.03.10.07.23.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 10 Mar 2018 07:23:33 -0800 (PST) From: Ard Biesheuvel To: linux-crypto@vger.kernel.org Cc: herbert@gondor.apana.org.au, linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Dave Martin , Russell King - ARM Linux , Sebastian Andrzej Siewior , Mark Rutland , linux-rt-users@vger.kernel.org, Peter Zijlstra , Catalin Marinas , Will Deacon , Steven Rostedt , Thomas Gleixner Subject: [PATCH v5 21/23] crypto: arm64/sha512-ce - yield NEON after every block of input Date: Sat, 10 Mar 2018 15:22:06 +0000 Message-Id: <20180310152208.10369-22-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180310152208.10369-1-ard.biesheuvel@linaro.org> References: <20180310152208.10369-1-ard.biesheuvel@linaro.org> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Avoid excessive scheduling delays under a preemptible kernel by conditionally yielding the NEON after every block of input. Signed-off-by: Ard Biesheuvel --- arch/arm64/crypto/sha512-ce-core.S | 27 +++++++++++++++----- 1 file changed, 21 insertions(+), 6 deletions(-) -- 2.15.1 diff --git a/arch/arm64/crypto/sha512-ce-core.S b/arch/arm64/crypto/sha512-ce-core.S index 7f3bca5c59a2..ce65e3abe4f2 100644 --- a/arch/arm64/crypto/sha512-ce-core.S +++ b/arch/arm64/crypto/sha512-ce-core.S @@ -107,17 +107,23 @@ */ .text ENTRY(sha512_ce_transform) + frame_push 3 + + mov x19, x0 + mov x20, x1 + mov x21, x2 + /* load state */ - ld1 {v8.2d-v11.2d}, [x0] +0: ld1 {v8.2d-v11.2d}, [x19] /* load first 4 round constants */ adr_l x3, .Lsha512_rcon ld1 {v20.2d-v23.2d}, [x3], #64 /* load input */ -0: ld1 {v12.2d-v15.2d}, [x1], #64 - ld1 {v16.2d-v19.2d}, [x1], #64 - sub w2, w2, #1 +1: ld1 {v12.2d-v15.2d}, [x20], #64 + ld1 {v16.2d-v19.2d}, [x20], #64 + sub w21, w21, #1 CPU_LE( rev64 v12.16b, v12.16b ) CPU_LE( rev64 v13.16b, v13.16b ) @@ -196,9 +202,18 @@ CPU_LE( rev64 v19.16b, v19.16b ) add v11.2d, v11.2d, v3.2d /* handled all input blocks? */ - cbnz w2, 0b + cbz w21, 3f + + if_will_cond_yield_neon + st1 {v8.2d-v11.2d}, [x19] + do_cond_yield_neon + b 0b + endif_yield_neon + + b 1b /* store new state */ -3: st1 {v8.2d-v11.2d}, [x0] +3: st1 {v8.2d-v11.2d}, [x19] + frame_pop ret ENDPROC(sha512_ce_transform)