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[209.132.180.67]) by mx.google.com with ESMTP id q16si2824191pfg.221.2018.03.10.07.23.34; Sat, 10 Mar 2018 07:23:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ADy9E1gc; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932369AbeCJPXc (ORCPT + 1 other); Sat, 10 Mar 2018 10:23:32 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:55902 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932359AbeCJPX2 (ORCPT ); Sat, 10 Mar 2018 10:23:28 -0500 Received: by mail-wm0-f67.google.com with SMTP id q83so8911793wme.5 for ; Sat, 10 Mar 2018 07:23:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=apZ9QsQuaZ0gT1OVIfDzjvRv8DsDf/pTY8gsd2Y7Oiw=; b=ADy9E1gcBwO+tYFBIPdbEqonckWhwCTH9638nxOgpLPvKJFFRI3dNPLIpXMZSAfs6T uOHqZnoMRsKzh2XScaBoYIVmOTiPijXsUHm1v7NmsWrLsqRVW+r3C+FliEknLYzbfoxW HpDUab2hwO8N1+ZRCQXS8BEPMu4VDfEfZtnnI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=apZ9QsQuaZ0gT1OVIfDzjvRv8DsDf/pTY8gsd2Y7Oiw=; b=BcBdp2tgJr+RLpnYcPmZWV3ITSyRt2UIq5z94yimAQV0qi5hi7du9JlWxY93xZhEPU fMZrgjl/1Fie4TIbPmAlzzjEEO/D0Zei2iQnt7xn7bt3UHLCjiK0ILXVcOTytooe9Trm PVUt4KzXmaN4oIgw6sIi6TeiThUAcKHHVj7mTkOCoeln+bU1HIJJlnW5fmsoGF6fOfYm 638OUOo9EpYDFhHq/x0gbmA7g9GAT5ODGqglvDDZtbpDF4I7MQZCRw/dUlcMVxst5LAQ IojPpF9K2Uw299OJOWdMLO5HvYCL4f8tKd+2mWYB75F1br/Z/opTe09T4R0pjgIFjyK5 b1wA== X-Gm-Message-State: AElRT7GEE2efsYFuUb0Nj1rHcACV0lCR5rQ/X1wOaStEv/iDxs5b4bsg 5uN3DnDaPOCpfyvl63K1OQQD9POUzco= X-Received: by 10.28.85.7 with SMTP id j7mr1259212wmb.38.1520695407432; Sat, 10 Mar 2018 07:23:27 -0800 (PST) Received: from localhost.localdomain ([105.148.128.186]) by smtp.gmail.com with ESMTPSA id m9sm7027531wrf.13.2018.03.10.07.23.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 10 Mar 2018 07:23:26 -0800 (PST) From: Ard Biesheuvel To: linux-crypto@vger.kernel.org Cc: herbert@gondor.apana.org.au, linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Dave Martin , Russell King - ARM Linux , Sebastian Andrzej Siewior , Mark Rutland , linux-rt-users@vger.kernel.org, Peter Zijlstra , Catalin Marinas , Will Deacon , Steven Rostedt , Thomas Gleixner Subject: [PATCH v5 19/23] crypto: arm64/crct10dif-ce - yield NEON after every block of input Date: Sat, 10 Mar 2018 15:22:04 +0000 Message-Id: <20180310152208.10369-20-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180310152208.10369-1-ard.biesheuvel@linaro.org> References: <20180310152208.10369-1-ard.biesheuvel@linaro.org> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Avoid excessive scheduling delays under a preemptible kernel by conditionally yielding the NEON after every block of input. Signed-off-by: Ard Biesheuvel --- arch/arm64/crypto/crct10dif-ce-core.S | 32 +++++++++++++++++--- 1 file changed, 28 insertions(+), 4 deletions(-) -- 2.15.1 diff --git a/arch/arm64/crypto/crct10dif-ce-core.S b/arch/arm64/crypto/crct10dif-ce-core.S index f179c01bd55c..663ea71cdb38 100644 --- a/arch/arm64/crypto/crct10dif-ce-core.S +++ b/arch/arm64/crypto/crct10dif-ce-core.S @@ -74,13 +74,19 @@ .text .cpu generic+crypto - arg1_low32 .req w0 - arg2 .req x1 - arg3 .req x2 + arg1_low32 .req w19 + arg2 .req x20 + arg3 .req x21 vzr .req v13 ENTRY(crc_t10dif_pmull) + frame_push 3, 128 + + mov arg1_low32, w0 + mov arg2, x1 + mov arg3, x2 + movi vzr.16b, #0 // init zero register // adjust the 16-bit initial_crc value, scale it to 32 bits @@ -175,8 +181,25 @@ CPU_LE( ext v12.16b, v12.16b, v12.16b, #8 ) subs arg3, arg3, #128 // check if there is another 64B in the buffer to be able to fold - b.ge _fold_64_B_loop + b.lt _fold_64_B_end + + if_will_cond_yield_neon + stp q0, q1, [sp, #.Lframe_local_offset] + stp q2, q3, [sp, #.Lframe_local_offset + 32] + stp q4, q5, [sp, #.Lframe_local_offset + 64] + stp q6, q7, [sp, #.Lframe_local_offset + 96] + do_cond_yield_neon + ldp q0, q1, [sp, #.Lframe_local_offset] + ldp q2, q3, [sp, #.Lframe_local_offset + 32] + ldp q4, q5, [sp, #.Lframe_local_offset + 64] + ldp q6, q7, [sp, #.Lframe_local_offset + 96] + ldr_l q10, rk3, x8 + movi vzr.16b, #0 // init zero register + endif_yield_neon + + b _fold_64_B_loop +_fold_64_B_end: // at this point, the buffer pointer is pointing at the last y Bytes // of the buffer the 64B of folded data is in 4 of the vector // registers: v0, v1, v2, v3 @@ -304,6 +327,7 @@ _barrett: _cleanup: // scale the result back to 16 bits lsr x0, x0, #16 + frame_pop ret _less_than_128: