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[209.132.180.67]) by mx.google.com with ESMTP id i16si2382524pgv.496.2017.12.06.11.44.37; Wed, 06 Dec 2017 11:44:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=joUDHC6m; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752319AbdLFTog (ORCPT + 1 other); Wed, 6 Dec 2017 14:44:36 -0500 Received: from mail-wm0-f68.google.com ([74.125.82.68]:46873 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752320AbdLFTo0 (ORCPT ); Wed, 6 Dec 2017 14:44:26 -0500 Received: by mail-wm0-f68.google.com with SMTP id r78so9289330wme.5 for ; Wed, 06 Dec 2017 11:44:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nmrHmpQAJW1RNoM8S8w0VHO1J/XgSbx51edTYJDyDvE=; b=joUDHC6mHRG/9mBhWTxw6p5sBmBfeCgyYM+PIXSEioU8UireBx3eTFx5c2GjyjUmYM 94y5CN+VewAtkzsEi6eEnjgUyxAvV05IeyyRHmKLJRWA1HYbfGTPS4V8+Mxa1ALa7MML bFPG8K+LgfcKLcJLuPiF+E/kjrtUk8ctLzESc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nmrHmpQAJW1RNoM8S8w0VHO1J/XgSbx51edTYJDyDvE=; b=ObUylB/+ZQb/FoJsKjQtHyTIXNMzrTPYaUFC7eIg5rpgUIlcrIzehGEmPxkP7EsH0q kYJzPadydpPSBqg0OKZzBA1dTQQ/s5nsYcbVOLluztOvISPGQI/skiB3K5WIttCWS3gI pExU81/s8FLi0NxX9sTr9SUV9YbZ2/951H6V6sWnRAhy2Ru9FwlovXMZolBYuVoiQLX0 Db/kF0gBQRSqUq7MFMN1HO1IZUUV5To5PhCxwsf+eMXEN1QVAVRBXuCaRq/8a+FxAvuT 67iOjA5C0u/qJOohXJTLC9XpqS/oxF/ko/TJUEy6btBfxvLnDt+H5TlxzAQ4mKJRAUbB gOIA== X-Gm-Message-State: AKGB3mJQMQ4wNToO34/E59ATwj60t5M1PWjjXrkrPaNINY/whUDUK8ST y7/wGmNiJ6Wrre/WVH3pIyiWsfOlaVc= X-Received: by 10.28.170.75 with SMTP id t72mr8781612wme.15.1512589464864; Wed, 06 Dec 2017 11:44:24 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id b66sm3596594wmh.32.2017.12.06.11.44.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Dec 2017 11:44:24 -0800 (PST) From: Ard Biesheuvel To: linux-crypto@vger.kernel.org Cc: herbert@gondor.apana.org.au, linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Dave Martin , Russell King - ARM Linux , Sebastian Andrzej Siewior , Mark Rutland , linux-rt-users@vger.kernel.org, Peter Zijlstra , Catalin Marinas , Will Deacon , Steven Rostedt , Thomas Gleixner Subject: [PATCH v3 10/20] arm64: assembler: add utility macros to push/pop stack frames Date: Wed, 6 Dec 2017 19:43:36 +0000 Message-Id: <20171206194346.24393-11-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171206194346.24393-1-ard.biesheuvel@linaro.org> References: <20171206194346.24393-1-ard.biesheuvel@linaro.org> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org We are going to add code to all the NEON crypto routines that will turn them into non-leaf functions, so we need to manage the stack frames. To make this less tedious and error prone, add some macros that take the number of callee saved registers to preserve and the extra size to allocate in the stack frame (for locals) and emit the ldp/stp sequences. Signed-off-by: Ard Biesheuvel --- arch/arm64/include/asm/assembler.h | 60 ++++++++++++++++++++ 1 file changed, 60 insertions(+) -- 2.11.0 diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index aef72d886677..5f61487e9f93 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -499,6 +499,66 @@ alternative_else_nop_endif #endif .endm + /* + * frame_push - Push @regcount callee saved registers to the stack, + * starting at x19, as well as x29/x30, and set x29 to + * the new value of sp. Add @extra bytes of stack space + * for locals. + */ + .macro frame_push, regcount:req, extra + __frame st, \regcount, \extra + .endm + + /* + * frame_pop - Pop @regcount callee saved registers from the stack, + * starting at x19, as well as x29/x30. Also pop @extra + * bytes of stack space for locals. + */ + .macro frame_pop, regcount:req, extra + __frame ld, \regcount, \extra + .endm + + .macro __frame, op, regcount:req, extra=0 + .ifc \op, st + stp x29, x30, [sp, #-((\regcount + 3) / 2) * 16 - \extra]! + mov x29, sp + .endif + .if \regcount < 0 || \regcount > 10 + .error "regcount should be in the range [0 ... 10]" + .endif + .if (\extra % 16) != 0 + .error "extra should be a multiple of 16 bytes" + .endif + .if \regcount > 1 + \op\()p x19, x20, [sp, #16] + .if \regcount > 3 + \op\()p x21, x22, [sp, #32] + .if \regcount > 5 + \op\()p x23, x24, [sp, #48] + .if \regcount > 7 + \op\()p x25, x26, [sp, #64] + .if \regcount > 9 + \op\()p x27, x28, [sp, #80] + .elseif \regcount == 9 + \op\()r x27, [sp, #80] + .endif + .elseif \regcount == 7 + \op\()r x25, [sp, #64] + .endif + .elseif \regcount == 5 + \op\()r x23, [sp, #48] + .endif + .elseif \regcount == 3 + \op\()r x21, [sp, #32] + .endif + .elseif \regcount == 1 + \op\()r x19, [sp, #16] + .endif + .ifc \op, ld + ldp x29, x30, [sp], #((\regcount + 3) / 2) * 16 + \extra + .endif + .endm + /* * Errata workaround post TTBR0_EL1 update. */