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[209.132.180.67]) by mx.google.com with ESMTP id d23si10177768pfe.339.2017.12.04.04.27.37; Mon, 04 Dec 2017 04:27:37 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=OaPVCwB6; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753271AbdLDM1f (ORCPT + 1 other); Mon, 4 Dec 2017 07:27:35 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:44559 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753260AbdLDM1c (ORCPT ); Mon, 4 Dec 2017 07:27:32 -0500 Received: by mail-wm0-f67.google.com with SMTP id t8so5455482wmc.3 for ; Mon, 04 Dec 2017 04:27:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=rZXeGMBOOCqXYLCtDRFIOa9MhRvenoqWmRAqEcgLXII=; b=OaPVCwB6LlyiqdsakcOELuyj73LBJVykzdKu5xH7OuNkiElOvi3LoFdaj2c1fqbwve /q8iHyXcRl1AeWF03LGrN4tsao1Casn9WzpX6UJcwyFSmrNFy0qujDdtej04GfKVs5oN o5cZjNn4W8l/vumtsynIXsGOwkvopMNOUDFpE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rZXeGMBOOCqXYLCtDRFIOa9MhRvenoqWmRAqEcgLXII=; b=A1fjsto+uyj42r8OfKDz0dVqossvIw+YAt4WOAUkYLZBJFPP1ufQFo2GRa7gGdJhUf TM1pYO67/iNgDu0jUoeMhbV2CTq6HnksmiDp56XfOIDmgmIKZso5XVPB2CCHsIuL57mI t351zVbWPRbpKXhJWtLKVCWX06vGCooQ9p+0XKmjIYlffwO+2HcG3gzVGFjPUxbt9oKu IllVQjJe5Bils77aIvVqiEqNFGZMU9HI3IokDkH/cqvHZKdUvuET97s3+ubPHXx6d7NS geGSVpmfEEh6GR6sSy0akWwlgRr2MJzRhVPozKtloMLNLyXZMC3CiVL2hBo4zHWrN07n jl+Q== X-Gm-Message-State: AKGB3mJj2OvHwsG8c7brwyWBIx9pZPk6L6ezK2nLkqbJzVE1pNpJNYkh F0wAojTf5iTiLL8Yxo5qpdUfwH+xihM= X-Received: by 10.28.110.24 with SMTP id j24mr6624027wmc.100.1512390451014; Mon, 04 Dec 2017 04:27:31 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id a8sm7665839wmh.41.2017.12.04.04.27.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Dec 2017 04:27:30 -0800 (PST) From: Ard Biesheuvel To: linux-crypto@vger.kernel.org Cc: herbert@gondor.apana.org.au, linux-arm-kernel@lists.infradead.org, Ard Biesheuvel , Dave Martin , Russell King - ARM Linux , Sebastian Andrzej Siewior , Mark Rutland , linux-rt-users@vger.kernel.org, Peter Zijlstra , Catalin Marinas , Will Deacon , Steven Rostedt , Thomas Gleixner Subject: [PATCH v2 12/19] crypto: arm64/sha1-ce - yield every 8 blocks of input Date: Mon, 4 Dec 2017 12:26:38 +0000 Message-Id: <20171204122645.31535-13-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171204122645.31535-1-ard.biesheuvel@linaro.org> References: <20171204122645.31535-1-ard.biesheuvel@linaro.org> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Avoid excessive scheduling delays under a preemptible kernel by yielding the NEON every 8 blocks of input. Signed-off-by: Ard Biesheuvel --- arch/arm64/crypto/sha1-ce-core.S | 45 ++++++++++++++------ 1 file changed, 32 insertions(+), 13 deletions(-) -- 2.11.0 diff --git a/arch/arm64/crypto/sha1-ce-core.S b/arch/arm64/crypto/sha1-ce-core.S index 8550408735a0..7ae0dd369e0a 100644 --- a/arch/arm64/crypto/sha1-ce-core.S +++ b/arch/arm64/crypto/sha1-ce-core.S @@ -70,31 +70,40 @@ * int blocks) */ ENTRY(sha1_ce_transform) + stp x29, x30, [sp, #-48]! + mov x29, sp + stp x19, x20, [sp, #16] + str x21, [sp, #32] + + mov x19, x0 + mov x20, x1 + mov x21, x2 + /* load round constants */ - adr x6, .Lsha1_rcon +0: adr x6, .Lsha1_rcon ld1r {k0.4s}, [x6], #4 ld1r {k1.4s}, [x6], #4 ld1r {k2.4s}, [x6], #4 ld1r {k3.4s}, [x6] /* load state */ - ld1 {dgav.4s}, [x0] - ldr dgb, [x0, #16] + ld1 {dgav.4s}, [x19] + ldr dgb, [x19, #16] /* load sha1_ce_state::finalize */ ldr_l w4, sha1_ce_offsetof_finalize, x4 - ldr w4, [x0, x4] + ldr w4, [x19, x4] /* load input */ -0: ld1 {v8.4s-v11.4s}, [x1], #64 - sub w2, w2, #1 +1: ld1 {v8.4s-v11.4s}, [x20], #64 + sub w21, w21, #1 CPU_LE( rev32 v8.16b, v8.16b ) CPU_LE( rev32 v9.16b, v9.16b ) CPU_LE( rev32 v10.16b, v10.16b ) CPU_LE( rev32 v11.16b, v11.16b ) -1: add t0.4s, v8.4s, k0.4s +2: add t0.4s, v8.4s, k0.4s mov dg0v.16b, dgav.16b add_update c, ev, k0, 8, 9, 10, 11, dgb @@ -125,16 +134,23 @@ CPU_LE( rev32 v11.16b, v11.16b ) add dgbv.2s, dgbv.2s, dg1v.2s add dgav.4s, dgav.4s, dg0v.4s - cbnz w2, 0b + cbz w21, 3f + + yield_neon_pre w21, 3, 1, 1b // yield every 8 blocks + st1 {dgav.4s}, [x19] + str dgb, [x19, #16] + yield_neon_post 0b + + b 1b /* * Final block: add padding and total bit count. * Skip if the input size was not a round multiple of the block size, * the padding is handled by the C code in that case. */ - cbz x4, 3f +3: cbz x4, 4f ldr_l w4, sha1_ce_offsetof_count, x4 - ldr x4, [x0, x4] + ldr x4, [x19, x4] movi v9.2d, #0 mov x8, #0x80000000 movi v10.2d, #0 @@ -143,10 +159,13 @@ CPU_LE( rev32 v11.16b, v11.16b ) mov x4, #0 mov v11.d[0], xzr mov v11.d[1], x7 - b 1b + b 2b /* store new state */ -3: st1 {dgav.4s}, [x0] - str dgb, [x0, #16] +4: st1 {dgav.4s}, [x19] + str dgb, [x19, #16] + ldp x19, x20, [sp, #16] + ldr x21, [sp, #32] + ldp x29, x30, [sp], #48 ret ENDPROC(sha1_ce_transform)