From patchwork Mon Apr 13 09:58:04 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Corentin Labbe X-Patchwork-Id: 197882 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C0BFCC352B6 for ; Mon, 13 Apr 2020 10:05:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9C46020776 for ; Mon, 13 Apr 2020 10:05:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20150623.gappssmtp.com header.i=@baylibre-com.20150623.gappssmtp.com header.b="hRBo1G3D" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728505AbgDMKFH (ORCPT ); Mon, 13 Apr 2020 06:05:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728282AbgDMKEu (ORCPT ); Mon, 13 Apr 2020 06:04:50 -0400 Received: from mail-wm1-x341.google.com (mail-wm1-x341.google.com [IPv6:2a00:1450:4864:20::341]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 578DFC00860E for ; Mon, 13 Apr 2020 02:58:21 -0700 (PDT) Received: by mail-wm1-x341.google.com with SMTP id d77so8825194wmd.3 for ; Mon, 13 Apr 2020 02:58:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2ZHpZbFZ++v3cKfeP7IKeimNT4Vuw4UtFR8orhFaF4c=; b=hRBo1G3DOK/DNnBWriz8Qmr/5ELKf6P/Rcos9wZl4ih/o3LnifiQlU48ElXb7Okdv3 N/3eHhZqC5Pdp4tPGSuttepjg0I/hVUWqU9P2+4M0L9qRPUDP0XAlt346frl6CCIPjWk Wplk6aYXE8HiQPa3iPC9OSI7cZTDgMlD/I1RDxSSZjCH7izNzPEZzWS8X68kpMFa+gS/ TZNC0YpLYANnohr8tLMeloMptAAMn2PKbixEB7DOpCwbWN1qAMLLtDPwjWTp0EShNQ4r nHlbyNbD5YyiTqXw4iCwidWCjHuzlOjRLDoQ9Ob4GjtlOBv+maVwtrWGlCL1gJRgFdGe HtOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2ZHpZbFZ++v3cKfeP7IKeimNT4Vuw4UtFR8orhFaF4c=; b=eOBLWVzGt6oui4QKIGXJsltR/bLocimYNv6h30slulTeOznaKEHmetkI72kBG6G9hZ 3v8gHgqxAB8TDh8mcJUm7fx8tu91Q5ISxQsyazrqeL7xVxJJn8toY/6FBFSK1XAQ2bPt QtAU3LuztW6gXYlckHmlI5muQB81lRGQtsPyHKIzaEN5rWRqpdkM+Rvt8PBo+VKnp3AS 3SOS5INTyXRiR+r55r2k2dOIjhnuPk5dLyTRmt4LFPfqt5yXNPtJcDbPOJ3ZAV5zDxyR NkinQGNwGQARyRuxAhenwZxZSsMaJmUQR0/jQg6NhmSYpInQlJ2k54tEF5oIOnQhvXqw b1Mg== X-Gm-Message-State: AGi0Pub8sNZT63AS+oT3InW3ZGisnUN1bS5AHMMaYEzn8HcHCppN6FaK Gd7Jv5EvR/UQQhFu6GSsbvfSLw== X-Google-Smtp-Source: APiQypKJfDM02MzpKehm9IbMohayh50jUY1gysaerVZg07xeCVmQUtrLRxWhUhcfXQrVYRPR5JTVHg== X-Received: by 2002:a7b:cb03:: with SMTP id u3mr16902884wmj.12.1586771900003; Mon, 13 Apr 2020 02:58:20 -0700 (PDT) Received: from localhost.localdomain ([51.15.160.169]) by smtp.googlemail.com with ESMTPSA id v21sm13594491wmj.8.2020.04.13.02.58.19 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Apr 2020 02:58:19 -0700 (PDT) From: Corentin Labbe To: davem@davemloft.net, herbert@gondor.apana.org.au, mripard@kernel.org, wens@csie.org Cc: linux-arm-kernel@lists.infradead.org, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, Corentin Labbe Subject: [PATCH 4/9] crypto: sun8i-ce: handle different error registers Date: Mon, 13 Apr 2020 09:58:04 +0000 Message-Id: <1586771889-3299-5-git-send-email-clabbe@baylibre.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586771889-3299-1-git-send-email-clabbe@baylibre.com> References: <1586771889-3299-1-git-send-email-clabbe@baylibre.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Error registers are different across SoCs. This patch handle those difference. Signed-off-by: Corentin Labbe --- .../crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 58 ++++++++++++++++--- drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h | 8 +++ 2 files changed, 58 insertions(+), 8 deletions(-) diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c index 3e4e4bbda34c..dbe2e0c3a4f2 100644 --- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c +++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c @@ -40,7 +40,8 @@ static const struct ce_variant ce_h3_variant = { .ce_clks = { { "bus", 0, 200000000 }, { "mod", 50000000, 0 }, - } + }, + .esr = ESR_H3, }; static const struct ce_variant ce_h5_variant = { @@ -51,7 +52,8 @@ static const struct ce_variant ce_h5_variant = { .ce_clks = { { "bus", 0, 200000000 }, { "mod", 300000000, 0 }, - } + }, + .esr = ESR_H5, }; static const struct ce_variant ce_h6_variant = { @@ -64,7 +66,8 @@ static const struct ce_variant ce_h6_variant = { { "bus", 0, 200000000 }, { "mod", 300000000, 0 }, { "ram", 0, 400000000 }, - } + }, + .esr = ESR_H6, }; static const struct ce_variant ce_a64_variant = { @@ -75,7 +78,8 @@ static const struct ce_variant ce_a64_variant = { .ce_clks = { { "bus", 0, 200000000 }, { "mod", 300000000, 0 }, - } + }, + .esr = ESR_A64, }; static const struct ce_variant ce_r40_variant = { @@ -86,7 +90,8 @@ static const struct ce_variant ce_r40_variant = { .ce_clks = { { "bus", 0, 200000000 }, { "mod", 300000000, 0 }, - } + }, + .esr = ESR_R40, }; /* @@ -102,6 +107,7 @@ int sun8i_ce_run_task(struct sun8i_ce_dev *ce, int flow, const char *name) { u32 v; int err = 0; + struct ce_task *cet = ce->chanlist[flow].tl; #ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG ce->chanlist[flow].stat_req++; @@ -128,19 +134,52 @@ int sun8i_ce_run_task(struct sun8i_ce_dev *ce, int flow, const char *name) msecs_to_jiffies(ce->chanlist[flow].timeout)); if (ce->chanlist[flow].status == 0) { - dev_err(ce->dev, "DMA timeout for %s\n", name); + dev_err(ce->dev, "DMA timeout for %s (tm=%d) on flow %d\n", name, ce->chanlist[flow].timeout, flow); err = -EFAULT; } /* No need to lock for this read, the channel is locked so * nothing could modify the error value for this channel */ v = readl(ce->base + CE_ESR); - if (v) { + switch (ce->variant->esr) { + case ESR_H3: + /* Sadly, the error bit is not per flow */ + if (v) { + dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow); + err = -EFAULT; + print_hex_dump(KERN_INFO, "TASK: ", DUMP_PREFIX_NONE, 16, 4, cet, sizeof(struct ce_task), false); + } + if (v & CE_ERR_ALGO_NOTSUP) + dev_err(ce->dev, "CE ERROR: algorithm not supported\n"); + if (v & CE_ERR_DATALEN) + dev_err(ce->dev, "CE ERROR: data length error\n"); + if (v & CE_ERR_KEYSRAM) + dev_err(ce->dev, "CE ERROR: keysram access error for AES\n"); + break; + case ESR_A64: + case ESR_H5: + case ESR_R40: v >>= (flow * 4); + v &= 0xF; + if (v) { + dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow); + err = -EFAULT; + print_hex_dump(KERN_INFO, "TASK: ", DUMP_PREFIX_NONE, 16, 4, cet, sizeof(struct ce_task), false); + } + if (v & CE_ERR_ALGO_NOTSUP) + dev_err(ce->dev, "CE ERROR: algorithm not supported\n"); + if (v & CE_ERR_DATALEN) + dev_err(ce->dev, "CE ERROR: data length error\n"); + if (v & CE_ERR_KEYSRAM) + dev_err(ce->dev, "CE ERROR: keysram access error for AES\n"); + break; + case ESR_H6: + v >>= (flow * 8); v &= 0xFF; if (v) { dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow); err = -EFAULT; + print_hex_dump(KERN_INFO, "TASK: ", DUMP_PREFIX_NONE, 16, 4, cet, sizeof(struct ce_task), false); } if (v & CE_ERR_ALGO_NOTSUP) dev_err(ce->dev, "CE ERROR: algorithm not supported\n"); @@ -150,7 +189,10 @@ int sun8i_ce_run_task(struct sun8i_ce_dev *ce, int flow, const char *name) dev_err(ce->dev, "CE ERROR: keysram access error for AES\n"); if (v & CE_ERR_ADDR_INVALID) dev_err(ce->dev, "CE ERROR: address invalid\n"); - } + if (v & CE_ERR_KEYLADDER) + dev_err(ce->dev, "CE ERROR: key ladder configuration error\n"); + break; + } return err; } diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h index fe97fee74e47..ed1a91da967b 100644 --- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h +++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h @@ -65,6 +65,12 @@ #define CE_ERR_ADDR_INVALID BIT(5) #define CE_ERR_KEYLADDER BIT(6) +#define ESR_H3 0 +#define ESR_A64 1 +#define ESR_R40 2 +#define ESR_H5 3 +#define ESR_H6 4 + #define CE_DIE_ID_SHIFT 16 #define CE_DIE_ID_MASK 0x07 @@ -94,12 +100,14 @@ struct ce_clock { * @has_t_dlen_in_bytes: Does the request size for cipher is in * bytes or words * @ce_clks: list of clocks needed by this variant + * @esr: The type of error register */ struct ce_variant { char alg_cipher[CE_ID_CIPHER_MAX]; u32 op_mode[CE_ID_OP_MAX]; bool has_t_dlen_in_bytes; struct ce_clock ce_clks[CE_MAX_CLOCKS]; + int esr; }; struct sginfo {