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[209.132.180.67]) by mx.google.com with ESMTP id p61si4117021plb.5.2017.06.04.01.04.59; Sun, 04 Jun 2017 01:04:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-crypto-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-crypto-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751204AbdFDIEq (ORCPT + 1 other); Sun, 4 Jun 2017 04:04:46 -0400 Received: from foss.arm.com ([217.140.101.70]:52866 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751389AbdFDIEc (ORCPT ); Sun, 4 Jun 2017 04:04:32 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9FA3A344; Sun, 4 Jun 2017 01:04:31 -0700 (PDT) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [217.140.101.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A21423F589; Sun, 4 Jun 2017 01:04:29 -0700 (PDT) From: Gilad Ben-Yossef To: Greg Kroah-Hartman Cc: Joe Perches , Ofir Drang , linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org, driverdev-devel@linuxdriverproject.org, devel@driverdev.osuosl.org Subject: [PATCH v3 18/18] staging: ccree: remove descriptor context definitions Date: Sun, 4 Jun 2017 11:02:39 +0300 Message-Id: <1496563362-7954-19-git-send-email-gilad@benyossef.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1496563362-7954-1-git-send-email-gilad@benyossef.com> References: <1496563362-7954-1-git-send-email-gilad@benyossef.com> Sender: linux-crypto-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Remove definitions of descriptor context which are not used in the driver. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/ccree/cc_crypto_ctx.h | 86 ----------------------------------- 1 file changed, 86 deletions(-) -- 2.1.4 diff --git a/drivers/staging/ccree/cc_crypto_ctx.h b/drivers/staging/ccree/cc_crypto_ctx.h index 20f3f9f..591f6fd 100644 --- a/drivers/staging/ccree/cc_crypto_ctx.h +++ b/drivers/staging/ccree/cc_crypto_ctx.h @@ -196,91 +196,5 @@ enum drv_crypto_padding_type { DRV_PADDING_RESERVE32B = S32_MAX }; -/*******************************************************************/ -/***************** DESCRIPTOR BASED CONTEXTS ***********************/ -/*******************************************************************/ - - /* Generic context ("super-class") */ -struct drv_ctx_generic { - enum drv_crypto_alg alg; -} __attribute__((__may_alias__)); - -struct drv_ctx_hash { - enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_HASH */ - enum drv_hash_mode mode; - u8 digest[CC_DIGEST_SIZE_MAX]; - /* reserve to end of allocated context size */ - u8 reserved[CC_CTX_SIZE - 2 * sizeof(u32) - - CC_DIGEST_SIZE_MAX]; -}; - -/* NOTE! drv_ctx_hmac should have the same structure as drv_ctx_hash except - * k0, k0_size fields - */ -struct drv_ctx_hmac { - enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_HMAC */ - enum drv_hash_mode mode; - u8 digest[CC_DIGEST_SIZE_MAX]; - u32 k0[CC_HMAC_BLOCK_SIZE_MAX / sizeof(u32)]; - u32 k0_size; - /* reserve to end of allocated context size */ - u8 reserved[CC_CTX_SIZE - 3 * sizeof(u32) - - CC_DIGEST_SIZE_MAX - CC_HMAC_BLOCK_SIZE_MAX]; -}; - -struct drv_ctx_cipher { - enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_AES */ - enum drv_cipher_mode mode; - enum drv_crypto_direction direction; - enum drv_crypto_key_type crypto_key_type; - enum drv_crypto_padding_type padding_type; - u32 key_size; /* numeric value in bytes */ - u32 data_unit_size; /* required for XTS */ - /* block_state is the AES engine block state. - * It is used by the host to pass IV or counter at initialization. - * It is used by SeP for intermediate block chaining state and for - * returning MAC algorithms results. - */ - u8 block_state[CC_AES_BLOCK_SIZE]; - u8 key[CC_AES_KEY_SIZE_MAX]; - u8 xex_key[CC_AES_KEY_SIZE_MAX]; - /* reserve to end of allocated context size */ - u32 reserved[CC_DRV_CTX_SIZE_WORDS - 7 - - CC_AES_BLOCK_SIZE / sizeof(u32) - 2 * - (CC_AES_KEY_SIZE_MAX / sizeof(u32))]; -}; - -/* authentication and encryption with associated data class */ -struct drv_ctx_aead { - enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_AES */ - enum drv_cipher_mode mode; - enum drv_crypto_direction direction; - u32 key_size; /* numeric value in bytes */ - u32 nonce_size; /* nonce size (octets) */ - u32 header_size; /* finit additional data size (octets) */ - u32 text_size; /* finit text data size (octets) */ - u32 tag_size; /* mac size, element of {4, 6, 8, 10, 12, 14, 16} */ - /* block_state1/2 is the AES engine block state */ - u8 block_state[CC_AES_BLOCK_SIZE]; - u8 mac_state[CC_AES_BLOCK_SIZE]; /* MAC result */ - u8 nonce[CC_AES_BLOCK_SIZE]; /* nonce buffer */ - u8 key[CC_AES_KEY_SIZE_MAX]; - /* reserve to end of allocated context size */ - u32 reserved[CC_DRV_CTX_SIZE_WORDS - 8 - - 3 * (CC_AES_BLOCK_SIZE / sizeof(u32)) - - CC_AES_KEY_SIZE_MAX / sizeof(u32)]; -}; - -/*******************************************************************/ -/***************** MESSAGE BASED CONTEXTS **************************/ -/*******************************************************************/ - -/* Get the address of a @member within a given @ctx address - * @ctx: The context address - * @type: Type of context structure - * @member: Associated context field - */ -#define GET_CTX_FIELD_ADDR(ctx, type, member) ((ctx) + offsetof(type, member)) - #endif /* _CC_CRYPTO_CTX_H_ */