From patchwork Thu May 10 08:14:06 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Westin X-Patchwork-Id: 8514 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id E2DC423E49 for ; Thu, 10 May 2012 08:14:43 +0000 (UTC) Received: from mail-yw0-f52.google.com (mail-yw0-f52.google.com [209.85.213.52]) by fiordland.canonical.com (Postfix) with ESMTP id 9CA3FA18837 for ; Thu, 10 May 2012 08:14:43 +0000 (UTC) Received: by yhpp61 with SMTP id p61so1491058yhp.11 for ; Thu, 10 May 2012 01:14:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:from:to:cc :subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:x-gm-message-state; bh=GpEXqkYluFifpyRJdowfK94dwmaaWjzH87ai/s/kxc0=; b=GzkJc3K8CHkXqCEh/EpsV1W6eqvdL//u+OTk+NPBZp2SVLp7E4gnug1VMQwvDVyauW CG6KrfpNTpYVp5IBw6pzebF4Z22ZI7Rw3YE49wYf8GbGoUPGCPeJKd5UAcEKpLaeB34S bc0N7MItWhaRZ65aVJmeTn4da/PD3BuK25oe7esLtgV1QDDCUi+0HwNBX+XHYFTr5XqZ 2mGwzu8P54LAdIixa6MvHRMSBCnBdN0lcQIRBDCoLxzBgQLVx2c1WY5Dm8cHVqjz89Zl w3J/an18OKNjgQkeGJ+2w7QLvn1gWtZmVxsagiXO6ZnBL/PACz3sd5rL/TD066z6xEkS oG/A== Received: by 10.50.89.168 with SMTP id bp8mr1236657igb.3.1336637683019; Thu, 10 May 2012 01:14:43 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.73.147 with SMTP id q19csp75754ibj; Thu, 10 May 2012 01:14:42 -0700 (PDT) Received: by 10.14.96.6 with SMTP id q6mr635364eef.6.1336637680430; Thu, 10 May 2012 01:14:40 -0700 (PDT) Received: from eu1sys200aog115.obsmtp.com (eu1sys200aog115.obsmtp.com. [207.126.144.139]) by mx.google.com with SMTP id n3si1542363eeh.11.2012.05.10.01.14.37 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 10 May 2012 01:14:40 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.139 is neither permitted nor denied by best guess record for domain of andreas.westin@stericsson.com) client-ip=207.126.144.139; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.139 is neither permitted nor denied by best guess record for domain of andreas.westin@stericsson.com) smtp.mail=andreas.westin@stericsson.com Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob115.postini.com ([207.126.147.11]) with SMTP ID DSNKT6t45YAXdKB7jExnI5jny+r45djSiLII@postini.com; Thu, 10 May 2012 08:14:40 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 28BF359; Thu, 10 May 2012 08:13:57 +0000 (GMT) Received: from relay2.stm.gmessaging.net (unknown [10.230.100.18]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id AFCB366; Thu, 10 May 2012 05:51:45 +0000 (GMT) Received: from exdcvycastm004.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm004", Issuer "exdcvycastm004" (not verified)) by relay2.stm.gmessaging.net (Postfix) with ESMTPS id 76DD5A8098; Thu, 10 May 2012 10:14:10 +0200 (CEST) Received: from steludxu4049.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.2) with Microsoft SMTP Server (TLS) id 8.3.83.0; Thu, 10 May 2012 10:14:14 +0200 From: Andreas Westin To: Herbert Xu , "David S. Miller" Cc: , , , , , Andreas Westin Subject: [PATCH v2 1/3] mach-ux500: Crypto: core support for CRYP/HASH module. Date: Thu, 10 May 2012 10:14:06 +0200 Message-ID: <1336637648-10064-2-git-send-email-andreas.westin@stericsson.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1336637648-10064-1-git-send-email-andreas.westin@stericsson.com> References: <1336637648-10064-1-git-send-email-andreas.westin@stericsson.com> MIME-Version: 1.0 X-Gm-Message-State: ALoCoQk6SET9Hm5Ta1bIvQv2mzFtT/mikVUhHQxZbueoYgIy9lcVM37x/UBWVeRU07F7HUZLRQJF This adds the required platform data and calls to enable the CRYP/HASH driver. Acked-by: Linus Walleij Signed-off-by: Andreas Westin --- arch/arm/mach-ux500/board-mop500.c | 48 ++++++++++++++++++++ arch/arm/mach-ux500/clock.c | 18 ++++---- arch/arm/mach-ux500/devices-common.h | 54 +++++++++++++++++++++++ arch/arm/mach-ux500/devices-db8500.c | 3 ++ arch/arm/mach-ux500/devices-db8500.h | 4 ++ arch/arm/mach-ux500/include/mach/crypto-ux500.h | 1 + arch/arm/mach-ux500/include/mach/devices.h | 3 ++ arch/arm/mach-ux500/include/mach/hardware.h | 3 ++ 8 files changed, 126 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c index 77d03c1..d622606 100644 --- a/arch/arm/mach-ux500/board-mop500.c +++ b/arch/arm/mach-ux500/board-mop500.c @@ -47,6 +47,7 @@ #include #include #include +#include #include "pins-db8500.h" #include "ste-dma40-db8500.h" @@ -417,6 +418,45 @@ static void mop500_prox_deactivate(struct device *dev) regulator_put(prox_regulator); } +static struct cryp_platform_data u8500_cryp1_platform_data = { + .mem_to_engine = { + .dir = STEDMA40_MEM_TO_PERIPH, + .src_dev_type = STEDMA40_DEV_SRC_MEMORY, + .dst_dev_type = DB8500_DMA_DEV48_CAC1_TX, + .src_info.data_width = STEDMA40_WORD_WIDTH, + .dst_info.data_width = STEDMA40_WORD_WIDTH, + .mode = STEDMA40_MODE_LOGICAL, + .src_info.psize = STEDMA40_PSIZE_LOG_4, + .dst_info.psize = STEDMA40_PSIZE_LOG_4, + }, + .engine_to_mem = { + .dir = STEDMA40_PERIPH_TO_MEM, + .src_dev_type = DB8500_DMA_DEV48_CAC1_RX, + .dst_dev_type = STEDMA40_DEV_DST_MEMORY, + .src_info.data_width = STEDMA40_WORD_WIDTH, + .dst_info.data_width = STEDMA40_WORD_WIDTH, + .mode = STEDMA40_MODE_LOGICAL, + .src_info.psize = STEDMA40_PSIZE_LOG_4, + .dst_info.psize = STEDMA40_PSIZE_LOG_4, + } +}; + +static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = { + .dir = STEDMA40_MEM_TO_PERIPH, + .src_dev_type = STEDMA40_DEV_SRC_MEMORY, + .dst_dev_type = DB8500_DMA_DEV50_HAC1_TX, + .src_info.data_width = STEDMA40_WORD_WIDTH, + .dst_info.data_width = STEDMA40_WORD_WIDTH, + .mode = STEDMA40_MODE_LOGICAL, + .src_info.psize = STEDMA40_PSIZE_LOG_16, + .dst_info.psize = STEDMA40_PSIZE_LOG_16, +}; + +static struct hash_platform_data u8500_hash1_platform_data = { + .mem_to_engine = &u8500_hash_dma_cfg_tx, + .dma_filter = stedma40_filter, +}; + /* add any platform devices here - TODO */ static struct platform_device *mop500_platform_devs[] __initdata = { &mop500_gpio_keys_device, @@ -602,6 +642,12 @@ static void __init mop500_uart_init(struct device *parent) db8500_add_uart2(parent, &uart2_plat); } +static void __init u8500_cryp1_hash1_init(struct device *parent) +{ + db8500_add_cryp1(parent, &u8500_cryp1_platform_data); + db8500_add_hash1(parent, &u8500_hash1_platform_data); +} + static struct platform_device *snowball_platform_devs[] __initdata = { &snowball_led_dev, &snowball_key_dev, @@ -633,6 +679,8 @@ static void __init mop500_init_machine(void) mop500_spi_init(parent); mop500_uart_init(parent); + u8500_cryp1_hash1_init(parent); + i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c index ec35f0a..2efc1fe 100644 --- a/arch/arm/mach-ux500/clock.c +++ b/arch/arm/mach-ux500/clock.c @@ -382,14 +382,15 @@ static DEFINE_PRCC_CLK(5, usb, 0, 0, NULL); /* Peripheral Cluster #6 */ /* MTU ID in data */ -static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 8, -1, NULL, clk_mtu_get_rate, 1); -static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 7, -1, NULL, clk_mtu_get_rate, 0); -static DEFINE_PRCC_CLK(6, cfgreg, 6, 6, NULL); -static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); -static DEFINE_PRCC_CLK(6, unipro, 4, 1, &clk_uniproclk); -static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); -static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); -static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); +static DEFINE_PRCC_CLK_CUSTOM(6, mtu1, 9, -1, NULL, clk_mtu_get_rate, 1); +static DEFINE_PRCC_CLK_CUSTOM(6, mtu0, 8, -1, NULL, clk_mtu_get_rate, 0); +static DEFINE_PRCC_CLK(6, cfgreg, 7, 7, NULL); +static DEFINE_PRCC_CLK(6, hash1, 6, -1, NULL); +static DEFINE_PRCC_CLK(6, unipro, 5, 1, &clk_uniproclk); +static DEFINE_PRCC_CLK(6, pka, 4, -1, NULL); +static DEFINE_PRCC_CLK(6, hash0, 3, -1, NULL); +static DEFINE_PRCC_CLK(6, cryp0, 2, -1, NULL); +static DEFINE_PRCC_CLK(6, cryp1, 1, -1, NULL); static DEFINE_PRCC_CLK(6, rng, 0, 0, &clk_rngclk); static struct clk clk_dummy_apb_pclk = { @@ -431,6 +432,7 @@ static struct clk_lookup u8500_clks[] = { CLK(pka, "pka", NULL), CLK(hash0, "hash0", NULL), CLK(cryp0, "cryp0", NULL), + CLK(cryp1, "cryp1", NULL), /* PRCMU level clock gating */ diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h index 39c74ec..89c5a59 100644 --- a/arch/arm/mach-ux500/devices-common.h +++ b/arch/arm/mach-ux500/devices-common.h @@ -12,12 +12,17 @@ #include #include #include +#include extern struct amba_device * dbx500_add_amba_device(struct device *parent, const char *name, resource_size_t base, int irq, void *pdata, unsigned int periphid); +extern struct platform_device * +dbx500_add_platform_device_noirq(const char *name, int id, + resource_size_t base, void *pdata); + struct spi_master_cntlr; static inline struct amba_device * @@ -88,6 +93,55 @@ dbx500_add_rtc(struct device *parent, resource_size_t base, int irq) return dbx500_add_amba_device(parent, "rtc-pl031", base, irq, NULL, 0); } +struct cryp_platform_data; + +static inline struct platform_device * +dbx500_add_cryp1(struct device *parent, int id, resource_size_t base, int irq, + struct cryp_platform_data *pdata) +{ + struct resource res[] = { + DEFINE_RES_MEM(base, SZ_4K), + DEFINE_RES_IRQ(irq), + }; + + struct platform_device_info pdevinfo = { + .parent = parent, + .name = "cryp1", + .id = id, + .res = res, + .num_res = ARRAY_SIZE(res), + .data = pdata, + .size_data = sizeof(*pdata), + .dma_mask = DMA_BIT_MASK(32), + }; + + return platform_device_register_full(&pdevinfo); +} + +struct hash_platform_data; + +static inline struct platform_device * +dbx500_add_hash1(struct device *parent, int id, resource_size_t base, + struct hash_platform_data *pdata) +{ + struct resource res[] = { + DEFINE_RES_MEM(base, SZ_4K), + }; + + struct platform_device_info pdevinfo = { + .parent = parent, + .name = "hash1", + .id = id, + .res = res, + .num_res = ARRAY_SIZE(res), + .data = pdata, + .size_data = sizeof(*pdata), + .dma_mask = DMA_BIT_MASK(32), + }; + + return platform_device_register_full(&pdevinfo); +} + struct nmk_gpio_platform_data; void dbx500_add_gpios(struct device *parent, resource_size_t *base, int num, diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c index 6e66d37..91754a8 100644 --- a/arch/arm/mach-ux500/devices-db8500.c +++ b/arch/arm/mach-ux500/devices-db8500.c @@ -104,6 +104,8 @@ static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = { [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET, [DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET, [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET, + [DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET, + [DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET, }; /* Mapping between source event lines and physical device address */ @@ -139,6 +141,7 @@ static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = { [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET, [DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET, [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET, + [DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET, }; /* Reserved event lines for memcpy only */ diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h index 9fd93e9..cdf5ca8 100644 --- a/arch/arm/mach-ux500/devices-db8500.h +++ b/arch/arm/mach-ux500/devices-db8500.h @@ -124,4 +124,8 @@ db8500_add_ssp(struct device *parent, const char *name, resource_size_t base, dbx500_add_uart(parent, "uart2", U8500_UART2_BASE, \ IRQ_DB8500_UART2, pdata) +#define db8500_add_cryp1(parent, pdata) \ + dbx500_add_cryp1(parent, -1, U8500_CRYP1_BASE, IRQ_DB8500_CRYP1, pdata) +#define db8500_add_hash1(parent, pdata) \ + dbx500_add_hash1(parent, -1, U8500_HASH1_BASE, pdata) #endif diff --git a/arch/arm/mach-ux500/include/mach/crypto-ux500.h b/arch/arm/mach-ux500/include/mach/crypto-ux500.h index de40add..5b2d081 100644 --- a/arch/arm/mach-ux500/include/mach/crypto-ux500.h +++ b/arch/arm/mach-ux500/include/mach/crypto-ux500.h @@ -5,6 +5,7 @@ * License terms: GNU General Public License (GPL) version 2 */ #ifndef _CRYPTO_UX500_H +#define _CRYPTO_UX500_H #include #include diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h index 5f6cb71..a55454a 100644 --- a/arch/arm/mach-ux500/include/mach/devices.h +++ b/arch/arm/mach-ux500/include/mach/devices.h @@ -15,6 +15,9 @@ extern struct platform_device u8500_gpio_devs[]; extern struct amba_device ux500_pl031_device; +extern struct platform_device ux500_hash1_device; +extern struct platform_device ux500_cryp1_device; + extern struct platform_device u8500_dma40_device; extern struct platform_device ux500_ske_keypad_device; diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h index f846989..ac2353c 100644 --- a/arch/arm/mach-ux500/include/mach/hardware.h +++ b/arch/arm/mach-ux500/include/mach/hardware.h @@ -31,6 +31,9 @@ #include #define MSP_TX_RX_REG_OFFSET 0 +#define CRYP1_RX_REG_OFFSET 0x10 +#define CRYP1_TX_REG_OFFSET 0x8 +#define HASH1_TX_REG_OFFSET 0x4 #ifndef __ASSEMBLY__