From patchwork Sat Dec 18 01:08:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Wang X-Patchwork-Id: 525539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFAF0C433EF for ; Sat, 18 Dec 2021 01:09:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231578AbhLRBJE (ORCPT ); Fri, 17 Dec 2021 20:09:04 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:51892 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S229771AbhLRBJC (ORCPT ); Fri, 17 Dec 2021 20:09:02 -0500 X-UUID: 25bfb4c2a40b48e7a3642788b9dadd6c-20211218 X-UUID: 25bfb4c2a40b48e7a3642788b9dadd6c-20211218 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1903545254; Sat, 18 Dec 2021 09:08:58 +0800 Received: from mtkexhb02.mediatek.inc (172.21.101.103) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Sat, 18 Dec 2021 09:08:57 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkexhb02.mediatek.inc (172.21.101.103) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 18 Dec 2021 09:08:56 +0800 Received: from mtkswgap22.mediatek.inc (172.21.77.33) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 18 Dec 2021 09:08:55 +0800 From: To: , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , Mark Chen Subject: [PATCH 2/3] Bluetooth: btmtksdio: Enable SCO over I2S function Date: Sat, 18 Dec 2021 09:08:52 +0800 Message-ID: X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <632534014b9b8a38e81dfb5749dcd75e2088adb1.1639787634.git.objelf@gmail.com> References: <632534014b9b8a38e81dfb5749dcd75e2088adb1.1639787634.git.objelf@gmail.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-bluetooth@vger.kernel.org From: Mark Chen For MediaTek chipset, the driver has to issue the specific command to enable Bluetooth SCO support over the I2S/PCM interface. Co-developed-by: Sean Wang Signed-off-by: Sean Wang Signed-off-by: Mark Chen --- drivers/bluetooth/btmtk.h | 20 +++++++++ drivers/bluetooth/btmtksdio.c | 76 +++++++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) diff --git a/drivers/bluetooth/btmtk.h b/drivers/bluetooth/btmtk.h index 2be1d2680ad8..fc57ef09d132 100644 --- a/drivers/bluetooth/btmtk.h +++ b/drivers/bluetooth/btmtk.h @@ -7,8 +7,12 @@ #define HCI_WMT_MAX_EVENT_SIZE 64 +#define BTMTK_WMT_REG_WRITE 0x1 #define BTMTK_WMT_REG_READ 0x2 +#define MT7921_PINMUX_0 0x70005050 +#define MT7921_PINMUX_1 0x70005054 + enum { BTMTK_WMT_PATCH_DWNLD = 0x1, BTMTK_WMT_TEST = 0x2, @@ -76,6 +80,22 @@ struct btmtk_wakeon { __le16 wakeup_delay; } __packed; +struct btmtk_sco { + u8 clock_config; + u8 transmit_format_config; + u8 channel_format_config; + u8 channel_select_config; +} __packed; + +struct reg_write_cmd { + u8 type; + u8 rsv; + u8 num; + __le32 addr; + __le32 data; + __le32 mask; +} __packed; + struct btmtk_hci_wmt_params { u8 op; u8 flag; diff --git a/drivers/bluetooth/btmtksdio.c b/drivers/bluetooth/btmtksdio.c index 771733ce362b..8e4d8c2da824 100644 --- a/drivers/bluetooth/btmtksdio.c +++ b/drivers/bluetooth/btmtksdio.c @@ -830,6 +830,74 @@ static int btsdio_mtk_reg_read(struct hci_dev *hdev, u32 reg, u32 *val) return err; } +static int btsdio_mtk_reg_write(struct hci_dev *hdev, u32 reg, u32 val, u32 mask) +{ + struct btmtk_hci_wmt_params wmt_params; + struct reg_write_cmd reg_write = { + .type = 1, + .num = 1, + .addr = cpu_to_le32(reg), + .data = cpu_to_le32(val), + .mask = cpu_to_le32(mask), + }; + int err, status; + + wmt_params.op = BTMTK_WMT_REGISTER; + wmt_params.flag = BTMTK_WMT_REG_WRITE; + wmt_params.dlen = sizeof(reg_write); + wmt_params.data = ®_write; + wmt_params.status = &status; + + err = mtk_hci_wmt_sync(hdev, &wmt_params); + if (err < 0) + bt_dev_err(hdev, "Failed to write reg(%d)", err); + + return err; +} + +static int btsdio_mtk_sco_setting(struct hci_dev *hdev) +{ + struct btmtk_sco sco_setting = { + .clock_config = 0x49, + .channel_format_config = 0x80, + }; + struct sk_buff *skb; + u32 val; + int err; + + /* Enable SCO over i2s/pcm for Mediatek Chipset */ + skb = __hci_cmd_sync(hdev, 0xfc72, sizeof(sco_setting), + &sco_setting, HCI_CMD_TIMEOUT); + if (IS_ERR(skb)) + return PTR_ERR(skb); + + err = btsdio_mtk_reg_read(hdev, MT7921_PINMUX_0, &val); + if (err < 0) { + bt_dev_err(hdev, "Failed to read register (%d)", err); + return err; + } + + val |= 0x11000000; + err = btsdio_mtk_reg_write(hdev, MT7921_PINMUX_0, val, ~0); + if (err < 0) { + bt_dev_err(hdev, "Failed to write register (%d)", err); + return err; + } + + err = btsdio_mtk_reg_read(hdev, MT7921_PINMUX_1, &val); + if (err < 0) { + bt_dev_err(hdev, "Failed to read register (%d)", err); + return err; + } + + val |= 0x00000101; + err = btsdio_mtk_reg_write(hdev, MT7921_PINMUX_1, val, ~0); + if (err < 0) + bt_dev_err(hdev, "Failed to write register (%d)", err); + + return err; +} + static int btmtksdio_setup(struct hci_dev *hdev) { struct btmtksdio_dev *bdev = hci_get_drvdata(hdev); @@ -862,6 +930,14 @@ static int btmtksdio_setup(struct hci_dev *hdev) err = mt79xx_setup(hdev, fwname); if (err < 0) return err; + + /* Enable sco over i2s/pcm */ + err = btsdio_mtk_sco_setting(hdev); + if (err < 0) { + bt_dev_err(hdev, "Failed to enable sco setting (%d)", err); + return err; + } + break; case 0x7663: case 0x7668: