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[209.132.180.67]) by mx.google.com with ESMTP id k6-v6si427746pls.426.2018.09.12.02.53.29; Wed, 12 Sep 2018 02:53:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QxsYTz7w; spf=pass (google.com: best guess record for domain of linux-arm-msm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-arm-msm-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726819AbeILO5O (ORCPT + 13 others); Wed, 12 Sep 2018 10:57:14 -0400 Received: from mail-ed1-f66.google.com ([209.85.208.66]:44682 "EHLO mail-ed1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726810AbeILO5O (ORCPT ); Wed, 12 Sep 2018 10:57:14 -0400 Received: by mail-ed1-f66.google.com with SMTP id s10-v6so1233520edb.11 for ; Wed, 12 Sep 2018 02:53:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=ZveZRZ6ez2WFXt4vWZSNreLB4c6rXEn4jTnJUKvsQDk=; b=QxsYTz7wjLzAywPKeME/lb8Kr8KJSddcqY8CX2VtPjYdD8sXXSX1X4DuI0Rj7+/Ij1 LeU55vndWr0mBFKqCMwePkISgioxpm3ga2vVaqwJxehCslUgTO/6f3LPJqh8XdtJsG2D em7bAXoBOxPifhvgQrTGzKstdmo8MhwIUQlrQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=ZveZRZ6ez2WFXt4vWZSNreLB4c6rXEn4jTnJUKvsQDk=; b=GnXZ4+DRUcplf8aXIOVDClx0dhQasYHtlt+K3/s7+oYzQNz0UzCp1bZSaZsjCFb1iA 71fBUao61HkbQJGAbmVOAu2KXvqbaoZQ1WSmuKdRshfa45L4KjDzjfsrnW0WrjBWyBtU bTIe5ZqgQM8ulOwh9/0Sui5l5+Ek9kU/qgvNuquF5wswVVBTJuHkGkX1LZlWVzPsIJUb ivLaE+VLlsH1U/cZqVuIyVXwTOGdfoAbkDn7ZKTE5EbH1dotpKxkdD5e9fVbrmZooqGm oNdjADwjawphaMGKCQjB3FqZ3vFP++YNzbZcvwCexTVlyfpmcUKQGdeewbSuwGxUZEGk Zk2Q== X-Gm-Message-State: APzg51DZIWvhtbeQSppLAbT46ocMbYNkfbTlRguSDlVHWUGrVr5NWnx+ JiGbNrUodQ5YAYtatA/BLo9Dfw== X-Received: by 2002:a50:f297:: with SMTP id f23-v6mr1870386edm.40.1536746006441; Wed, 12 Sep 2018 02:53:26 -0700 (PDT) Received: from localhost ([49.248.190.214]) by smtp.gmail.com with ESMTPSA id a33-v6sm433189eda.2.2018.09.12.02.53.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Sep 2018 02:53:25 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org Cc: rnayak@codeaurora.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, smohanad@codeaurora.org, andy.gross@linaro.org, dianders@chromium.org, mka@chromium.org, Zhang Rui , Daniel Lezcano , linux-pm@vger.kernel.org Subject: [PATCH v3 01/16] thermal: tsens: Prepare 8916 and 8974 tsens to use SROT and TM address space Date: Wed, 12 Sep 2018 15:22:46 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org We've already converted over the devicetree of platforms using v2 version of the TSENS IP to use two address spaces. Now prepare to convert over the 8916 and 8974 platforms to use separate SROT and TM address spaces. This patch will work with device trees with one or two address spaces because we set the tm_offset in commit 5b1283984fa3 ("thermal: tsens: Add support to split up register address space into two"). Signed-off-by: Amit Kucheria Reviewed-by: Matthias Kaehlcke --- drivers/thermal/qcom/tsens-common.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 6207d8d92351..478739543bbc 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -21,7 +21,7 @@ #include #include "tsens.h" -#define S0_ST_ADDR 0x1030 +#define STATUS_OFFSET 0x30 #define SN_ADDR_OFFSET 0x4 #define SN_ST_TEMP_MASK 0x3ff #define CAL_DEGC_PT1 30 @@ -107,8 +107,9 @@ int get_temp_common(struct tsens_device *tmdev, int id, int *temp) unsigned int status_reg; int last_temp = 0, ret; - status_reg = S0_ST_ADDR + s->hw_id * SN_ADDR_OFFSET; + status_reg = tmdev->tm_offset + STATUS_OFFSET + s->hw_id * SN_ADDR_OFFSET; ret = regmap_read(tmdev->map, status_reg, &code); + if (ret) return ret; last_temp = code & SN_ST_TEMP_MASK;